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? 3 sts-3/stm-1 to 1.544 mbit/s and 2.048 mbit/s add/drop mux/demux unidirectional or bidirectional ring applications sts-3/stm-1 termination terminal mode multiplexer sts-3/stm-1 test equipment document number: product preview txc-04218-mb, ed. 1 august 2003 data sheet product preview u.s. and/or foreign patents issued or pending copyright ? 2003 transwitch corporation phast, temx28, transwitch and txc are registered trademarks of transwitch corporation proprietary transwitch corporation information for use solely by its customers temx8 device 8 channel dual bus mapper txc-04218 add/drop up to 8 e1, ds1, or vt/tu payloads from two add and two drop stm-1/vc4, sts-3 buses add bus and drop bus timing modes cross mapping applications (ds1 mapped to/from vt2/tu-12s) selectable hdb3/b8zs/ami positive/negative rail, nrz, or vt/tu interfaces per channel h4 multiframe option in place of telecom bus v1 pulse digital desynchronizer drop buses are monitored for parity, loss of clock, and upstream ais performance counters for pointer movements, bip-2 errors, rei and coding violations single-bit or three-bit rdi operation per channel tandem connection capability per etsi standards j2 trail trace comparison option processor access to h1/h2, h4 overhead bytes, and v1/v2 and v4 bytes selectable positive, negative or positive/negative alarm transition interrupt options line and facility loopbacks, generation of bip-2 and rei errors, prbs generator and analyzer per channel polling registers and global summary alarm status one second measurements: counters and alarms software device driver is provided ieee 1149.1 standard boundary scan +3.3 v and 1.8 v power supplies, 5 v tolerant i/o leads 376-lead plastic ball grid array (pbga) package (23 mm x 23 mm) +3.3 v a - side drop bus desynchronizer clock a - side add bus b - side drop bus b - side add bus channel 1 (up to) microprocessor interface stm-1/sts-3 sdh/sonet side line side controls boundary scan temx8 dual bus mapper txc-04218 8 channel channel 8 e1 or ds1 lines +1.8 v the temx8 device is designed for add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. up to 8 e1, ds1, or vt/tu payloads are mapped to and from vt1.5/tu-11s and vt2/tu-12s carried in an stm-1 vc-4 or sts-3 format. the device interfaces to a multiple-segment, byte-parallel sdh/sonet-formatted bus at the 19.44 mbyte/s byte rate. the e1 and ds1 signals can be hdb3 or b8zs/ami rail signals, or nrz signals. the vt/tu interface can be provided with or without the overhead bytes for virtual concatenation applications. the temx8 performs pointer tracking and overhead byte processing, including single-bit or three-bit rdi operation, and optional tandem connection capability. all overhead bytes, including the v1/v2/v4 bytes, are provided for microprocessor access. the temx8 can generate receive and transmit line ais, transmit unequipped and supervisory unequipped channels, and transmit vt/tu ais, in addition to standards-compliant overhead byte monitoring. it also provides test features and a microprocessor interface. applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
temx8 txc-04218 - 2 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 table of contents section page list of figures................................................................................................................ .................... 3 overview ....................................................................................................................... .................... 4 features ....................................................................................................................... ..................... 5 block diagram .................................................................................................................. ................. 9 block diagram description ...................................................................................................... ........ 10 application example ............................................................................................................ ............ 16 interoperability............................................................................................................... ........... 16 lead diagram................................................................................................................... ............... 17 lead descriptions.............................................................................................................. .............. 18 absolute maximum ratings and environmental limitations ........................................................... 28 thermal characteristics........................................................................................................ ........... 28 power requirements............................................................................................................. .......... 28 input, output and input/output parameters .................................................................................... 2 9 timing characteristics ......................................................................................................... ............ 32 operation...................................................................................................................... ................... 51 bus interface modes ............................................................................................................ .... 51 bus mode selection ............................................................................................................. .... 52 sdh/sonet add/drop multiplexing format selections .......................................................... 52 drop and add tu/vt selection ................................................................................................ 53 bus timing ..................................................................................................................... .......... 54 performance counters ........................................................................................................... .. 54 alarm structure ................................................................................................................ ........ 54 one second (shadow) registers............................................................................................. 55 interrupt structure ............................................................................................................ ........ 56 drop bus interface ............................................................................................................. ...... 60 drop bus parity selection ...................................................................................................... .. 60 drop bus multiframe alignment................................................................................................ 6 1 sdh/sonet ais detection ..................................................................................................... 62 tu/vt pointer tracking......................................................................................................... ... 63 overhead byte processing ...................................................................................................... 66 overhead communications bit access .................................................................................... 72 overhead byte insertion ........................................................................................................ .. 77 test functions................................................................................................................. ......... 86 prbs pattern generator and analyzer.................................................................................... 86 resets ......................................................................................................................... ............. 87 data throughput delay .......................................................................................................... .. 88 pointer leak rate calculations................................................................................................ 89 jitter measurements............................................................................................................ ..... 90 boundary scan.................................................................................................................. ....... 99 multiplex format and mapping information ............................................................................ 101 memory map ..................................................................................................................... ............ 109 memory map descriptions........................................................................................................ ..... 122 package information ............................................................................................................ ......... 220 ordering information ........................................................................................................... .......... 221 related products............................................................................................................... ............ 221 reference documents............................................................................................................ ....... 222 standards documentation sources............................................................................................... 223 please note that transwitch provides documentation for al l of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com . customers who are using a transwitch product, or planning to do so, shoul d register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product.
temx8 txc-04218 - 3 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 list of figures figure page 1 temx8 txc-04218 block diagram .......................................................................................... 9 2 1544 kbit/s asynchronous mapping........................................................................................ 13 3 2048 kbit/s asynchronous mapping........................................................................................ 14 4 vc-11 to vc-12 cross mapping ............................................................................................. 15 5 application using the temx8 txc-04218 .............................................................................. 16 6 temx8 txc-04218 376-lead plastic ball grid array package lead diagram ...................... 17 7 channels 1 - 8 ds1/e1 transmit rail interface timing.......................................................... 32 8 channels 1 - 8 ds1/e1 transmit nrz interface timing......................................................... 33 9 channels 1 - 8 transmit vt/tu interface timing -gapped pointer bytes.............................. 34 10 channels 1 - 8 transmit vt/tu interface timing-gapped pointer & poh byte .................... 35 11 channels 1 - 8 ds1/e1 receive rail timing.......................................................................... 36 12 channels 1 - 8 ds1/e1 receive nrz timing......................................................................... 37 13 channels 1 - 8 receive vt/tu interface timing -gapped pointer bytes............................... 38 14 channels 1 - 8 receive vt/tu interface timing-gapped pointer & poh byte ..................... 39 15 sts-3 a/b drop and add bus signals, timing derived from drop bus (lead abte low) .................................................................... 40 16 sts-3 a/b drop and add bus signals, timing derived from drop bus (lead abte high) ................................................................... 41 17 stm-1 vc-4 a/b drop and add bus signals, timing derived from drop bus (lead abte low) .................................................................... 42 18 stm-1 vc-4 a/b drop and add bus signals, timing derived from drop bus (lead abte high) ................................................................... 43 19 sts-3 a/b add bus signals, timing derived from add bus .................................................. 44 20 stm-1 vc-4 a/b add bus signals, timing derived from add bus ........................................ 45 21 microprocessor read cycle timing - intel.............................................................................. 46 22 microprocessor write cycle timing - intel .............................................................................. 47 23 microprocessor read cycle timing - motorola ...................................................................... 48 24 microprocessor write cycle timing - motorola ...................................................................... 49 25 boundary scan timing ......................................................................................................... .. 50 26 alarm latching configurations ............................................................................................... 55 27 one second (shadow) register operation ............................................................................ 56 28 channel polling alarms ....................................................................................................... ... 57 29 global indication alarms..................................................................................................... .... 58 30 hardware interrupt indication ................................................................................................ . 59 31 h4 byte floating vt mode bit allocation................................................................................ 61 32 vt/tu pointer tracking state machine .................................................................................. 64 33 loopback, line ais and prbs generator/analyzer .............................................................. 87 34 e1 (2048 kbit/s) jitter tolerance............................................................................................ . 90 35 ds1 (1544 kbit/s) jitter tolerance .......................................................................................... 90 36 jitter tolerance measurements .............................................................................................. 9 1 37 jitter transfer .............................................................................................................. ........... 92 38 e1 jitter transfer measurements ........................................................................................... 93 39 ds1 jitter transfer measurements......................................................................................... 93 40 tu-12 standard pointer test sequences............................................................................... 96 41 vt1.5 standard pointer test sequences ............................................................................... 98 42 boundary scan schematic ................................................................................................... 10 0 43 temx8 txc-04218 376-lead plastic ball grid array package............................................ 220
temx8 txc-04218 - 4 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 overview the temx8 device is designed for add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. up to 8 e1, ds1, or vt/tu payloads are mapped to and from vt1.5/tu-11s and vt2/tu-12s carried in an stm-1 vc-4 or sts-3 format. the device interfaces to a multiple-segment, byte-parallel sdh/sonet-formatted bus at the 19.44 mbyte/s byte rate. the e1 and ds1 signals can be hdb3 or b8zs/ami positive/negative rail (dual unipolar) signals, or nrz signals. the vt/tu interface can be provided with or without the overhead bytes for virtual concatenation applications. the temx8 performs pointer tracking and overhead byte processing, including single-bit or three-bit rdi operation, and optional tandem connection capability. all overhead bytes, including the v1/v2/v4 bytes, are provided for microprocessor access. the temx8 can generate receive and transmit line ais, transmit unequipped and supervisory unequipped channels, and transmit vt/tu ais, in addition to standards-compliant overhead byte monitoring. for testing, the device provides ieee 1149.1 boundary scan, a prbs generator and analyzer, and both line and facility loopbacks. the temx8 supports split bus access for either intel or motorola microprocessors. its performance counters can be configured to be either saturating or roll over. interrupts can be generated by alarms that latch on positive, negative, or both positive and negative status transitions, and they can be dis- abled via mask bits. a software polling register and summary alarm bit status are also provided. one second measurements are performed for alarms and counters.
temx8 txc-04218 - 5 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 features the following is a detailed list of features supported by the temx8: bus modes of operation (each channel) drop mode only drop from a or b add mode only add to a or b add to a and b single unidirectional ring drop from a, add to a drop from b, add to b multiplexer drop from a, add to b drop from b, add to a dual protection ring drop from a, add to a and b drop from b, add to b and a bus timing drop bus timing add bus timing derived from the same named drop bus add bus timing add bus timing is independent of the drop bus lead selectable sonet/sdh combus interface drop bus timing enabled drop bus: c1j1v1, spe, byte wide data, clock, parity add bus: byte wide data, parity, add indicator option: clock, c1j1v1, and spe are outputs add bus timing enabled drop bus: c1j1v1, spe, byte wide data, clock, parity add bus: clock, c1j1v1, spe are inputs; byte wide data, parity, add indicator are outputs. mappings maximum of up to 8 channels ds1/e1 line asynchronous formats, or vc-11/vc-12s independent vt1.5/tu-11 or vt2/tu12 selection per channel for both drop and add buses cross mapping: ds1 mapped into vt1.5/tu-12 sonet/sdh operating formats sts-3 sts-1 (19.44 mbyte/s) stm-1 vc-4/tug-3/tug-2 (19.44 mbyte/s) stm-1 au-3s (19.44 mbyte/s)
temx8 txc-04218 - 6 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 other bus features drop buses input parity check with alarm indication odd, or even data only, or bus signals input loss of clock detection stuck high or low add buses output parity generation odd, or even data only, or bus signals add to bus indicator high z output bus signals control individual channel high z vt/tu time slots sonet/sdh features in-band upstream ais detection h1/h2 pointer bytes e1 bytes using majority voting h4 byte multiframe detectors or v1 pulse (c1j1v1) reference input determines location of v1/v2 pointer bytes pointer tracking etsi/itu/ansi state machine wrong size bits detection positive/negative justification 8-bit counters microprocessor access to v1/v2 pointer bytes (each channel) h4 poh bytes (both buses, vc-4 or three sts-1s) e1 (used for upstream ais indication) bytes (both buses, vc-4 or three sts-1s) h1/h2 pointer bytes (both buses, vc-4 or three sts-1s) vt/tu overhead byte processing j2 byte 64 byte read segment with optional cr/lf alignment 16 byte read segment with optional trail trace message comparison v5/k4 byte three bit or single bit rdi (programmable for each channel) detection/recovery selection: 5 or 10 event option rei error counter rfi detector bip-2 bit/block error counter option signal label mismatch, unequipped, and vc ais detection detection/recovery: 5 events n2 byte tandem connection option trail trace message comparison against microprocessor written message
temx8 txc-04218 - 7 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 overhead byte access both a and b buses desynchronizer meets ansi/etsi/itu requirements pointer test sequences jitter/mtie external clock (common to both rates) leak rate control microprocessor control - 10 bits line ais (ds1/e1) generation mask bits for individual alarms global mask bit for all alarms microprocessor control vt/tu overhead byte insertion (per channel) j2 byte 64 or 16 byte microprocessor written message j2 forced to 0 option v5/k4 byte rei insertion (from drop side vt/tu) rfi value from microprocessor bip-2 calculation and insertion rdi insertion single or three bit rdi generated for a minimum of 20 multiframes mask bits for alarms global mask bit for all alarms microprocessor control k4 byte input bits 1 and 2 from external vt/tu interface n2 byte tandem connection option 16 byte message insertion mask alarm bits or microprocessor for tc odi and rdi generation internal multiframe generation tc ais generation tc unequipped generation overhead single byte insertion all bytes test purpose unequipped generation (per channel) supervisory unequipped generation option transmit ais generation
temx8 txc-04218 - 8 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 tu/vt ais microprocessor control ds1 or e1 ais alarms with mask bits microprocessor control o-bit access drop and add both a and b buses line interface nrz external loss of signal or coding violation input rail codec ami/b8zs/hdb3 coding violation counter loss of signal detector vt/tu interface add bus timing mode only fixed c1j1 locations in add direction two modes: with or without (gapped clock) overhead bytes transmit direction: fixed framing references and clock outputs, data in bits 1 and 2 in k4 byte clocked in with data for symmetrical clock microprocessor interface intel or motorola split bus lds lead option (683xx processors) ready/dtack leads interrupt structure positive, negative, positive/negative alarm transitions polling registers with mask bits alarm summary bits with mask bits one second measurements counters roll over or saturating one second measurements test features boundary scan ds-1/e1 loopbacks facility line combus loopback high z all leads (except boundary scan output) prbs generator and analyzer 2 15 -1 as defined in o.151 and t1m1.3/92-006r3 or qrss (2 20 -1) as defined in ansi t1.403-1195) drop or add direction placement single bit error generation for transmit rei and bip-2
temx8 txc-04218 - 9 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 block diagram a block diagram of the temx8 device is shown in figure 1 . further information on device operation and the interfaces to external circuits is provided in the following paragraphs. figure 1. temx8 txc-04218 block diagram microprocessor interface drop bus interface address data control memory and drop bus signals bus a drop bus signals bus b add bus signals bus a add bus signals bus b drop pointer tracking n tu/vts drop overhead byte processing n tu/vts drop tc byte processing n tu/vts destuff desynchronizer drop bus interface drop pointer tracking n tu/vts drop overhead byte processing n tu/vts drop tc byte processing n tu/vts destuff desynchronizer add bus interface add bus interface ch n receive interface rdi/rei select drop side states for add channels tc states for add channels nrz rail vt rclkn rdatn rcon rvtcn rpon rvtdn rnon rvtfn select drop side map registers ram vt/tu payload vt/tu payload te s t port access tck tms tdi tdo trs reset test highz external desync clock stuff synchronizer construct tu insert oh bytes pointer generation stuff synchronizer construct tu insert oh bytes pointer generation ch n transmit interface nrz rail vt tclkn tdatn tcin tvtcn tpin tvtdn tnin vt frame pulses a vt frame pulses b tu/vt terminate tu/vt build a receive b receive b transmit a transmit tlosn
temx8 txc-04218 - 10 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 block diagram description as illustrated in figure 1 , the temx8 interfaces to four buses, designated as a drop, b drop, a add, and b add. the four buses run at the stm-1/sts-3 rate of 19.44 mbyte/s. for north american applications, asynchronous ds1 signals are carried in a floating virtual tributary 1.5 (vt1.5) format, while e1 signals are carried in a floating virtual tributary 2 (vt2) format. a maximum of 28 vt1.5 and 21 vt2 signals are carried in a synchronous transport signal - 1 (sts-1) format. three sts-1s are in turn carried in a sts-3 signal. for itu-t applications, asynchronous e1 signals are carried in floating mode tributary unit - 12 (tu-12) format and ds1 signals are carried in floating mode tributary unit - 11 (tu-11) format. the tu-12s and tu-11s are carried in an stm-1 virtual container - 4 (vc-4) structure using tributary unit group - 3 (tug-3), or in the stm-1 virtual container - 3 (vc-3) structure using tributary unit group - 2 (tug-2) mapping schemes. up to 8 ds1 or e1 signals, or a combination of ds1 and e1 signals, can be dropped from one bus (a drop or b drop) to the ds1 or e1 lines. a maximum of 8 asynchronous ds1 or e1 signals are converted into tu-11/tu-12 or vt1.5/vt2 format and are added to either of the add buses, or both, depending upon the mode of operation. the temx8 can provide, on a per channel basis, the virtual container - 11 (vc-11), or the e1 virtual container - 12 (vc-12) formats in place of the ds1 or e1 signals for virtual concatenation applications. the vc format contains the payload and overhead bytes associated with the tu-11 and tu-12 formats. the temx8 also supports the cross mapping feature specified in itu recommendation g707. this feature enables a ds1 asynchronous line signal to be carried in a tu-12/vt2 payload. this feature is supported in the temx8 on a per channel basis. when the temx8 is configured for drop bus timing, the add buses are, by definition, byte- and multiframe-synchronous with their like-named drop buses, but are delayed by one or two byte times because of internal processing. for example, if a byte in the stm-1 virtual container - 4 (vc-4) structure using tributary unit group - 3 (tug-3), tu-12/vt2 is to be added to the a add bus, the time of its placement on the bus is derived from the a drop bus timing, and from software instructions specifying which tu/vt number is being added. note that the tu/vt a drop bus selection can be different from the a add bus selection. an option is provided which enables the dropped timing signals to be sent as outputs on the add bus. when the device is configured for add bus timing, the add bus, parity, and add indicator signals are derived from the input add bus clock, c1j1v1 and spe signals. in the drop (receive) direction, the a receive drop bus interface block is identical to the b receive block. the tu/vt terminate block, destuff block and desychronizer block are repeated 16 times, 8 for each side (a and b sides). the channel n receive interface blocks are repeated 8 times, one for each channel. the interface between a drop bus and the receive block consists of 12 input leads: a 19.44 mhz byte clock, byte-wide data, a c1j1 indicator which may be also carrying a v1 indication making the signal a c1j1v1 indicator, an spe indicator, and an odd/even parity bit. the drop c1j1v1 signal is used in conjunction with the drop spe signal to determine the location of the various bytes in the sonet/sdh format. a single j1 pulse identifies the starting location of the j1 byte in the vc-4 format, when the spe signal is high. three j1 pulses are provided for the sts-3 format, each identifying the starting location of the j1 byte in each of the three sts-1 signals. the temx8 can function with either a v1 pulse in the c1j1v1 signal, or it can use an internal h4 detector, for determining the location of the v1 byte. the v1 pulse location is used to determine the location of the pointer bytes v1 and v2. for stm-1 vc-4 operation, if the c1j1v1 signal is used, a one add or drop bus clock cycle wide pulse must occur every four frames and three drop bus clock cycles after the j1 pulse while the spe is high. the j1 pulse identifies the j1 byte location (defined as the starting location for the vc-4) in the poh bytes. in the next column (first clock cycle) all the rows are assigned as fixed stuff. similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. the next column (third clock cycle) defines the start of tug-3 a. this column is where the v1 pulse occurs every four frames. however, the actual v1 byte location is six clock cycles after the v1 pulse. for sts-3 operation, three v1 pulses must be present every four frames. each of the three v1 pulses must be present three clock cycles after the corresponding j1 pulse, when the spe signal is high.
temx8 txc-04218 - 11 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 each drop bus (a and b) is monitored for parity errors, loss of clock, h4 multiframe alignment if selected, and an upstream sdh/sonet ais indication. the temx8 can monitor either the toh e1 order wire bytes or the h1/h2 bytes for an upstream ais indication. each tu/vt terminate block (a and b side) performs pointer processing using the v1 and v2 bytes. the pointer bytes are monitored for loss of pointer, alarm indication signal (ais), and a new data flag (ndf). the pointer tracking process is based on etsi/itu-t standards, which also meets ansi requirements. pointer increments and decrements are also counted, and the size bits are monitored for the correct value. this block also processes and monitors the various alarms found in the four overhead bytes. these operations including signal label mismatch detection, unequipped status detection, bip-2 parity error detection and error counter, rei error counting, and single-bit or three-bit remote defect indications (rdi). the temx8 performs a 16-byte j2 trail trace comparison on the channels selected. for 64-byte messages, the bytes are stored in a memory map segment for a microprocessor read cycle. the device also provides the tu tandem connection feature and performs the 16-byte message comparison for the n2 (formerly known as z6) byte message. all vt/tu overhead bytes, eight overhead communications channel bits (o-bits), the v1/v2 pointer bytes, and the v4 byte for each channel are available for a microprocessor read cycle. also, the e1 order wire bytes, the h1/h2 pointer bytes, and the h4 bytes from the upstream circuitry are also available for a microprocessor read cycle. a control bit for each port selects the tu/vt from either the a drop or b drop bus. the tu/vt is destuffed in the destuff block using majority logic rules for the three sets of three justification control bits to determine if the two s-bits are data bits or frequency justification bits. the desynchronizer block removes the effects on the ds1 or e1 output of systemic jitter that might occur because of signal mappings and pointer movements in the network. the desynchronizer block is comprised of a pointer leak buffer and a loop buffer. the pointer leak buffer spaces bursts of pointer movements more gradually over time and can accept up to five consecutive pointer movements. the loop buffer consists of a digital loop filter, which is designed to track the frequency of the received signal and to remove both transmission and stuffing jitter. the channel n receive interface block of each channel provides either nrz data, positive and negative rail signal, or a vt/tu interface. receive data (towards the line), for each of the channels, can be clocked out on either rising or falling edges of the clock. in addition, a control bit is provided for forcing the data and clock signals to a high impedance state (tristate), or to the zero state. in the add (transmit) direction, the temx8 accepts a clock and either nrz data or positive and negative rail signals. data, for each of the channels, can be clocked in on either the falling or rising edge of the clock. in the nrz mode, an external loss of clock indication or external coding violations can be provided. for the rail signal, coding violations are counted, and there is a loss of signal detector. a ds1/e1 ais detector is also provided. each channel can also be configured for vt/tu interface for virtual concatenation data applications. when this interface is selected, a clock signal is provided for strobing in data for either the a or b bus. four framing pulses are also provided which define the starting location of the vt1.5/tu-11 and vt2/tu-12. an option is provided for including the four overhead bytes. however, except for bits 1 and 2 in the k4 bytes, the other bits are ignored. bits 1 and 2 in the k4 byte carry an extended signal label and information pertaining to the payload position within the virtual concatenation channel. the virtual concatenation channel will be assigned to n vt/tus based on the data bandwidth required for the application.
temx8 txc-04218 - 12 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 for a nrz or positive/negative rail transmit interface, the line signal is written into two fifos, one for add a side and the other for the b side, in one of the two stuff/synchronizer block pairs. threshold modulation is used for the frequency justification process. timing information from the a and b drop buses or from the a and b add buses is used to read the fifo and perform the tu/vt justification process. the synchronizer block permits tracking of an incoming signal having an average frequency offset as high as 120 ppm, and up to 1.5 ui of peak-to-peak jitter. since the temx8 supports two different network architectures (ds1 and e1), two sets of blocks are provided for each channel. the tu/vt a and b add bus selection can be different. the vt/tu add bus selection can be different from the drop vt/tu selection. a control bit, and transmit line alarms, can also generate ds1/e1 ais. the tu/vt build blocks format the tu/vt into an sts-3 or stm-1 structure for the asynchronous ds1 or e1 signals. the pointer value carried in the v1 and v2 bytes is transmitted with a fixed value of 78 for the vt1.5/tu-11 and 105 for the vt2/tu-12. transmit access is provided for the eight overhead communications channel bits (o-bits) via the microprocessor. the microprocessor also writes the signal label, and the value of the j2 message, either as a 16-byte or a 64-byte message. the temx8 provides the tu tandem connection feature for the tu-11 or tu-12, including the transmission of the 16-byte message and the various alarms associated with the tandem connection feature. the device provides either single-bit or three-bit rdi using the v5 and k4 bytes. local alarms, or the microprocessor, can generate the remote payload, server, or connectivity defect indications. the remote error indication (rei) is inserted from the bip-2 errors detected on the receive side, and bip-2 parity is generated for the v5 byte. control bits are provided for generating unequipped status, generating tu/vt ais, and inserting rei and bip-2 errors in the v5 byte. control bits are also provided that enable the microprocessor to insert overhead byte test values, including the v1/v2 pointer bytes and the v4 byte. the a transmit block is identical to the b transmit block. the interface between an add bus and a transmit block consists of three input leads and ten output leads, when the add bus timing mode is selected. the input leads are a byte clock, a c1j1v1 indicator, and an spe indicator. the output leads are byte-wide data, and a parity indicator, and an add-to-bus indicator signal. the add c1j1v1 signal is used in conjunction with the add spe signal to determine the location of the various bytes in the sonet/sdh format. when drop bus timing is selected, the output leads are byte-wide data, a parity indicator, and an add-to-bus indicator. the add bus clock, spe and c1j1v1 signals, which are derived from the drop bus, can disabled or provided. the selection is performed by a lead. the microprocessor input/output interface block consists of an intel- or motorola-compatible split address/data bus interface that provides access to assigned temx8 memory map addresses. interrupt capability, interrupt mask bits, alarm summary bits, and software polling bits are also provided. the alarms that cause the interrupt can be set on positive, negative, or both positive and negative transitions. control bits are provided which enable a facility or a line loopback. in addition, a prbs analyzer and generator are provided. a 2 15 -1 or 2 20 -1 prbs pattern is supported. the analyzer and generator can be used in the drop or add line direction for additional testing flexibility. the test access port (tap) block provides a five-lead boundary scan capability that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test. the temx8 software driver has the same architecture of the other transwitch device drivers such as the ml3m or temx28 software, and is meant to be easily integrated with them. the application software calls the driver functions to configure, control and manage the temx8 device. the device driver insulates the application from the internal details of the device register usage and provides a higher level of abstraction. particularly powerful are the default configurations provided within the driver that allow one single command to bring the device to operational mode.
temx8 txc-04218 - 13 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 2. 1544 kbit/s asynchronous mapping v5 r r r r r r i r j2 c 1 c 2 o o o o i r 24 bytes (1544 kbit/s data) n2 24 bytes (1544 kbit/s data) c 1 c 2 o o o o i r tu-11/vt1.5 v1 (pointer byte) v4 (reserved) v2 (pointer byte) v3 (action) 500 s 104 bytes i = information o = overhead communications c n = justification control s n = justification opportunity r = fixed stuff (set to 0) (febe) rfi l 1 l 2 l 3 rdi bit 1 8 1 path overhead (v5) byte signal label ndf s 1 s 2 ididididid v 1 v 2 new data flag normal = 0110, 1110, 0010, 0100 or 0111 new = 1001, 0001, 1101, 1011 or 1000 positive justification = invert five i-bits negative justification = invert five d-bits pointer range = 0 - 103 decimal size s 1 s 2 = 11 bip-2 bip-2 = bit interleaved parity (2 bits) rei = remote error indication (formerly febe, far end block error indication) rfi = remote failure indication l 1 l 2 l 3 = signal label rdi = remote defect indication (formerly ferf, far end receive failure indication) vc-11 108 bytes rei (ferf) 24 bytes (1544 kbit/s data) k4 c 1 c 2 r r r s 1 s 2 r 24 bytes (1544 kbit/s data) 26 bytes 26 bytes 26 bytes 26 bytes
temx8 txc-04218 - 14 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 3. 2048 kbit/s asynchronous mapping v5 r r r r r r r r 32 bytes (2048 kbit/s data) j2 c 1 c 2 o o o o r r c 1 c 2 r r r r r s 1 32 bytes (2048 kbit/s data) n2 (z6) 32 bytes (2048 kbit/s data) k4 (z7) c 1 c 2 o o o o r r tu-12/vt2 v1 (pointer byte) 35 bytes v4 (reserved) v2 (pointer byte) v3 (action) 35 bytes 35 bytes 35 bytes 500 s 140 bytes i = information o = overhead communications c n = justification control s n = justification opportunity r = fixed stuff (set to 0) (febe) rfi l 1 l 2 l 3 rdi bit 1 8 1 path overhead (v5) byte signal label ndf s 1 s 2 ididididid v 1 v 2 new data flag normal = 0110, 1110, 0010, 0100 or 0111 new = 1001, 0001, 1101, 1011 or 1000 positive justification = invert five i-bits negative justification = invert five d-bits pointer range = 0 - 139 decimal size s 1 s 2 = 10 bip-2 bip-2 = bit interleaved parity (2 bits) rei = remote error indication (formerly febe, far end block error indication) rfi = remote failure indication l 1 l 2 l 3 = signal label rdi = remote defect indication (formerly ferf, far end receive failure indication) r r r r r r r r 31 bytes (2048 kbit/s data) s 2 i i i i i i i r r r r r r r r vc-12 144 bytes r r r r r r r r r r r r r r r r rei (ferf)
temx8 txc-04218 - 15 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 4. vc-11 to vc-12 cross mapping v5 34 bytes (2048 kbit/s data) tu-12/vt2 v1 (pointer byte) 35 bytes v4 (reserved) v2 (pointer byte) v3 (action) 35 bytes 35 bytes 35 bytes 500 s when mapping a vc-11 in to a vc-12, the vc-11 is adapted by adding fixed stuff with even parity. vc-12 144 bytes v5 j2 n2 k4 fixed stuffed with even parity per g.707. j2 34 bytes (2048 kbit/s data) n2(z6) 34 bytes (2048 kbit/s data) k4(z7) 34 bytes (2048 kbit/s data)
temx8 txc-04218 - 16 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 application example the application diagram in figure 5 below shows a fully configured bidirectional add/drop fiber multiplexer. using the four-bus capability of the temx8, channels may be dropped from either direction with full time slot reuse in both directions. using only the b drop and the a add buses provides add/drop service back to the net- work source only, and eliminates the block marked ?east terminal? for a terminal configuration. figure 5. application using the temx8 txc-04218 interoperability the temx8 works directly with the following transwitch devices: - qt1f- plus (txc-03103) - t1fx8 (txc-03108) - e1fx8 (txc-03109) - qe1f- plus (txc-03114) - phast ? -3n (txc-06103) - temx28 ? -(txc-04222) - t3bwp (txc-06826) - tepro (txc-06830) temx8 txc-04218 stm-1 a drop up to 8 channels b drop b add microprocessor bus west terminal and bus drivers/receivers east terminal and bus drivers/receivers or sts-3 stm-1 or sts-3 phast ? -3n (txc-06103) phast ? -3n (txc-06103) temx8 txc-04218 up to 8 channels a add
temx8 txc-04218 - 17 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 lead diagram figure 6. temx8 txc-04218 376-lead plastic ball grid array package lead diagram 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 t r p m l k j h g f e d c b note: this is the bottom view. the leads are solder balls. see figure 43 for package information. some signal symbols have been abbreviated to fit the space available. the symbols are shown in full in the lead descriptions section. 16 n ab aa y v u w a 17 22 21 20 19 18 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd1 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 vdd2 nc gnd nc gnd nc gnd nc gnd gnd nc nc gnd nc nc nc nc gnd gnd gnd nc gnd gnd nc gnd gnd nc nc gnd nc gnd nc nc gnd nc gnd gnd nc nc gnd gnd gnd nc gnd nc nc gnd gnd nc nc gnd gnd nc gnd gnd nc nc gnd gnd nc nc gnd gnd nc nc gnd gnd nc gnd gnd gnd nc nc gnd nc nc gnd gnd nc gnd nc nc nc gnd nc gnd nc gnd nc gnd gnd nc gnd gnd nc gnd nc nc nc gnd gnd nc gnd nc nc gnd nc nc gnd gnd nc gnd gnd nc nc nc nc gnd tci8 nc gnd gnd tni7 tpi8 nc gnd rco7 tci7 rno8 tni8 tpi6 rpo7 tpi7 rco8 rpo1 tni1 tci2 rno3 rco4 tni4 tpi5 rno6 tni6 rpo8 rno1 rpo2 tni2 tpi3 rno4 rpo5 tci5 rco6 rno7 rco1 tci1 rno2 rpo3 tci3 tpi4 rco5 tni5 rpo6 tci6 tpi1 rco2 tpi2 rco3 tni3 rpo4 tci4 rno5 gnd bd0 bd6 ad7 bd3 bd5 ad6 bdc1j1 bd2 bd4 ad2 ad5 bdspe bd1 adc1j1 ad1 ad4 bdpar adpar adspe ad0 ad3 ba5 ba6 ba7 adclk ba1 ba3 ba4 bdclk baspe bac1j1 ba0 ba2 baclk bapar badd aa6 aa7 aa5 aa4 aa1 aa3 aa2 aa0 aaclk aac1j1 aaspe aadd highz pm1s test nc d5 d0 a11 a6 a1 trs nc d6 d1 a12 a7 a3 sel moto tms tck reset d7 d2 a13 a9 a5 a2 rd int gnd tdi nc d4 d3 a14 a10 a8 a4 a0 wr dsclk rdy testo testi testi testo testo testi abust abte testi testo tdo testi aapar vtfb2 vtfa2 vtfa15 vtfb15 bd7 gnd
temx8 txc-04218 - 18 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 lead descriptions power supply, ground and no connects symbol lead no. i/o/p * name/function vdd1 e7, e8, e11, e12, e15, e16, g5, g18, h5, h18, l5, l18, m5, m18, r5, r18, t5, t18, v7, v8, v11, v12, v15, v16 p vdd1: +1.8 volt supply voltage, 5%. vdd2 e6, e9, e10, e13, e14, e17, f5, f18, j5, j18, k5, k18, n5, n18, p5, p18, u5, u18, v6, v9, v10, v13, v14, v17 p vdd2: +3.3 volt supply voltage, 5%. this supply voltage should be powered up prior to the 1.8 v (vdd1) supply voltage or at the same time. this supply voltage must not go below vdd1 by more than 0.5 v at any time including power down. gnd a1, a2, a3, a5, a7, a10, a13, a18, a19, a20, a22, ab1, ab22, b2, b5, b6, b9, b11, b14, b16, b17, b20, b21, b22, c3, c7, c8, c10, c11, c12, c14, c15, c18, c19, c20, d4, d5, d6, d9, d10, d12, d13, d14, d17, d19, d21, d22, e18, e20, e5, f20, f22, g19, g21, h19, h21, h22, j9-j14, j20, k9-k14, k20, k21, l19, l22, l9-l14, m9-m14, m21, m22, n9-n14, n20, n21, p9-p14, p22, r21, r22, t22, v5, v18, w4, w19, y3, y20 p ground: 0 volt reference. nc a4, a6, a8, a9, a11, a12, a14, a15, a16, a17, a21, aa4, ab3, b3, b4, b7, b8, b10, b12, b13, b15, b18, b19, c4, c5, c6, c9, c13, c16, c17, c21, c22, d7, d8, d11, d15, d16, d18, d20, e19, e21, e22, f19, f21, g20, g22, h20, j19, j21, j22, k19, k22, l20, l21, m19, m20, n19, n22, p19, p20, p21, r20, t21, w6 no connect: nc leads are not to be connected, not even to another nc lead, but must be left floating. connection of these leads may impair performance or cause damage to the device. *note: i = input; o = output; p = power; t=tristate *see input, output and input/output parameters section below for type definitions.
temx8 txc-04218 - 19 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 a drop and a add bus i/o symbol lead no. i/o/p type * name/function adclk j2 i ttl3v a drop bus clock: this clock operates at 19.44 mhz for stm-1/sts-3 operation. a drop bus byte-wide data (ad7-ad0), the parity bit (adpar), spe indication (adspe), and the c1j1v1 indica- tion (adc1j1v1) are clocked in on falling edges of this clock. this clock may also be used for add bus timing and deriving the like-named add bus byte-wide data, add and tu/vt indications, and parity bits. adpar h1 i ttl3v a drop bus parity bit: a parity bit input signal representing the odd or even parity calculation for each data byte, spe, and c1j1v1 sig- nal from the drop bus, or the data byte only. ad(7-0) e1, f2, g3, h4, f1, g2, h3, j4 i ttl3v a drop bus data byte: byte-wide data that corresponds to the stm-1/sts-3 signal on the drop bus. the first bit received (dropped) corresponds to bit 7 which is lead e1. adspe h2 i ttl3v a drop bus spe indicator: a signal that is active high for each byte of the stm-1 vc-4 and sts-3/sts-1 spes, and low for overhead byte times. adc1j1(v1) g1 i ttl3v a drop bus c1j1v1 indications: an active high timing signal that carries stm-1/sts-3 frame and spe information. this signal works in conjunction with the adspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1 and sts-3 signals, when adspe signal is low. the j1 pulse identifies the starting location of the j1 byte in the stm-1 vc-4 signal when adspe is high. three j1 pulses identify the starting location for each of the three sts-1 sig- nals in the sts-3 signal. a single v1 pulse identifies the location for the v1/v2 bytes in the tug-3 within the vc-4. three v1 pulses iden- tify the location of the v1/v2 bytes within each of the three sts-1s. the v1 pulses may be absent. in which case the mapper will detect the starting location of the multiframe within the h4 byte. aaclk p4 i/o(t) ttl3v/ cmos3v 8ma a add bus clock: when the add bus timing mode is selected (lead abust is low), this input must be provided for add bus timing. this clock operates at 19.44 mhz for stm-1/sts-3 operation. the add bus spe indication (aaspe), and the c1j1v1 indication (aac1j1v1) are clocked in on falling edges of this clock. add bus byte-wide data (aa7-aa0), add indicator (aadd ), and the parity bit (aapar) are clocked out on rising edges of the clock during the time slots that correspond to the selected tu/vt. when drop bus timing is selected (lead abust is high), and lead abte is low, this clock, which is derived from the like-named drop bus is an output. when lead abte is high in the drop bus timing mode, this lead is disabled. aapar t1 o(t) cmos3v 8ma a add bus parity bit: an odd or even parity output signal that is calculated over the byte-wide add data. when drop bus timing is selected (lead abust is high), and lead abte is low, parity may be also calculated for the c1j1v1 and spe signals. this lead is only active when there is data being added to the add bus.
temx8 txc-04218 - 20 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 b drop and b add bus i/o aa(7-0) n1, m4, n2, n3, p1, p2, n4, p3 o(t) cmos3v 8ma a add bus data byte: byte-wide data that corresponds to the selected tu/vt. the first bit transmitted (added) corresponds to bit 7 which is lead n1. aaspe r2 i/o(t) ttl3v/ cmos3v 8ma a add bus spe indicator: when the add bus timing mode is selected, this signal must be provided for add bus timing. this signal must be high during each byte of the stm-1/sts-3 payload, and low during transport overhead byte times. when drop bus timing is selected (lead abust is high), and lead abte is low, this signal, which is derived from the like-named drop bus is an output. when lead abte is high in the drop bus timing mode, this lead is disabled. aac1j1(v1) r1 i/o(t) ttl3v/ cmos3v 8ma a add bus c1j1v1 indications: an active high timing signal that carries stm-1/sts-3 frame and spe information. this signal works in conjunction with the aaspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1 and sts-3 signals, when aaspe signal is low. the j1 pulse identifies the starting location of the j1 byte in the stm-1 vc-4 signal when adspe is high. three j1 pulses identify the starting location for each of the three sts-1 sig- nals in the sts-3 signal. a single v1 pulse identifies the starting location for the v1/v2 bytes in the tug-3 within the vc-4. three v1 pulses identify the starting location of the v1/v2 bytes within each of the three sts-1s. when drop bus timing is selected (lead abust is high), and lead abte is low, this signal, which is derived from the like-named drop bus is an output. when lead abte is high in the a drop bus timing mode, this lead is disabled. aadd r3 o cmos3v 8ma a add bus add data present indicator: this normally active low signal is present when output data to the a add bus is valid. it identi- fies the location of all of the tu/vt time slots being selected. when control bit addi (bit 0, register 03ah) is 1, the indicator is active high instead of active low. symbol lead no. i/o/p type name/function bdclk g4 i ttl3v b drop bus clock: this clock operates at 19.44 mhz for stm-1/sts-3 operation. a drop bus byte-wide data (bd7-bd0), the parity bit (bdpar), spe indication (bdspe), and the c1j1v1 indi- cation (badc1j1v1) are clocked in on falling edges of this clock. this clock may also be used for add bus timing and deriving the like-named add bus byte-wide data, add and tu/vt indications, and parity bits. bdpar d1 i ttl3v b drop bus parity bit: a parity bit input signal representing the odd or even parity calculation for each data byte, spe, and c1j1v1 sig- nal from the drop bus, or the data byte only. bd(7-0) d3, b1, e4, e3, c2, d2, c1, f4 i ttl3v b drop bus data byte: byte-wide data that corresponds to the stm-1/sts-3 signal on the drop bus. the first bit received (dropped) corresponds to bit 7 which is lead d3. symbol lead no. i/o/p type * name/function
temx8 txc-04218 - 21 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 bdspe f3 i ttl3v b drop bus spe indicator: a signal that is active high for each byte of the stm-1 vc-4 and sts-3/sts-1 spes, and low for over- head byte times. bdc1j1(v1) e2 i ttl3v b drop bus c1j1v1 indications: an active high timing signal that carries stm-1/sts-3 frame and spe information. this signal works in conjunction with the bdspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1 and sts-3 signals, when bdspe signal is low. the j1 pulse identifies the starting location of the j1 byte in the stm-1 vc-4 signal when bdspe is high. three j1 pulses identify the starting location for each of the three sts-1 sig- nals in the sts-3 signal. a single v1 pulse identifies the location for the v1/v2 bytes in the tug-3 within the vc-4. three v1 pulses identify the location of the v1/v2 bytes within each of the three sts-1s. the v1 pulses may be absent. in which case the mapper will detect the starting location of the multiframe within the h4 byte. baclk m1 i/o(t) ttl3v/ cmos3v 8ma b add bus clock: when the add bus timing mode is selected (lead abust is low), this input must be provided for add bus timing. this clock operates at 19.44 mhz for stm-1/sts-3 operation. the add bus spe indication (baspe), and the c1j1v1 indication (bac1j1v1) are clocked in on falling edges of this clock. add bus byte-wide data (ba7-ba0), add indicator (badd ), and the parity bit (bapar) are clocked out on rising edges of the clock during the time slots that correspond to the selected tu/vt. when drop bus timing is selected (lead abust is high), and lead abte is low, this clock, which is derived from the like-named drop bus is an output. when lead abte is high in the drop bus timing mode, this lead is disabled and forced to the high impedance state. bapar m2 o(t) cmos3v 8ma b add bus parity bit: an odd or even parity output signal that is calculated over the byte-wide add data. when drop bus timing is selected (lead abust is high), and lead abte is low, parity may be also calculated for the c1j1v1 and spe signals. this lead is only active when there is data being added to the add bus. ba(7-0) j3, k4, k3, j1, k2, l4, k1, l3 o(t) cmos3v 8ma b add bus data byte: byte-wide data that corresponds to the selected tu/vt. the first bit transmitted (added) corresponds to bit 7 which is lead j3. baspe l1 i/o(t) ttl3v/ cmos3v 8ma b add bus spe indicator: when the add bus timing mode is selected, this signal must be provided for add bus timing. this signal must be high during each byte of the stm-1/sts-3 payload, and low during transport overhead byte times. when drop bus timing is selected (lead abust is high), and lead abte is low, this signal, which is derived from the like-named drop bus is an output. when lead abte is high in the drop bus timing mode, this lead is disabled and forced to the high impedance state. symbol lead no. i/o/p type name/function
temx8 txc-04218 - 22 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n line interface (n = 1, up to 8) bac1j1(v1) l2 i/o(t) ttl3v/ cmos3v 8ma b add bus c1j1v1 indications: an active high timing signal that carries stm-1/sts-3 frame and spe information. this signal works in conjunction with the aaspe signal. the c1 pulse identifies the location of the first c1 byte in the stm-1 and sts-3 signals, when aaspe signal is low. the j1 pulse identifies the starting location of the j1 byte in the stm-1 vc-4 signal when adspe is high. three j1 pulses identify the starting location for each of the three sts-1 sig- nals in the sts-3 signal. a single v1 pulse identifies the starting location for the v1/v2 bytes in the tug-3 within the vc-4. three v1 pulses identify the starting location of the v1/v2 bytes within each of the three sts-1s. when drop bus timing is selected (lead abust is high), and lead abte is low, this signal, which is derived from the like-named drop bus is an output. when lead abte is high in the b drop bus timing mode, this lead is disabled and forced to the high impedance state. badd m3 o cmos3v 8ma b add bus add data present indicator: this normally active low signal is present when output data to the a add bus is valid. it identi- fies the location of all of the tu/vt time slots being selected. when control bit addi (bit 0, register 03ah) is 1, the indicator is active high instead of active low. symbol lead no. i/o/p type name/function rcon rclkn rvtcn (n=1-8) aa13, ab15, ab17, w16, y18, y21, u19, v22 o(t) cmos3v 4ma receive channel n rail, nrz, tu/vt output clock: a ds1, e1, or vt/tu clock output. data (rail or nrz) is clocked out on positive transitions of this clock when control bit rnclki (bit 3, register x+000h) is a 1. when control bit rnclki is a 0, data is clocked out on negative transitions of this clock. rcon is the e1/t1 rail clock (control bits rnlint1/0 (bits 7/6, register x+006h) are 10). rclkn is the nrz clock (control bits rnlint1/0 are 01). rvtcn is the tu/vt nrz clock (control bits rnlint1/0 are 11). this lead is disabled when control bits rnlint1/0 are 00. when disabled, this lead can be forced to ether a high impedance state (control bit rnoutl (bit 5, regis- ter 006h) is a 0), or to zeros (control bit rnoutl is a 1). lead aa13 is rco1/rclk1/rvtc1 (channel 1). note: see description for control bit rnoutl for detailed operation. rpon rdatn rvtdn (n=1-8) w12, y14, aa16, ab19, aa19, aa21, v20, w22 o(t) cmos3v 4ma receive channel n data positive rail, nrz, tu/vt: when control bits rnlint1/0 are set to 10, positive rail e1/t1 data (rpon) is provided on this lead. when control bit rnlint1/0 is set to 01, nrz e1/t1 data (rdatn) is provided on this lead. when control bits rnlint1/0 are set to 11, vt/tu nrz data (rvtdn) is provided on this lead. this lead is disabled when control bits rnlint1/0 are 00. when disabled, this lead can be forced to ether a high impedance state (control bit rnoutl is a 0), or to zeros (control bit rnoutl is a 1). lead w12 is rpo1/rdat1/rvtd1 (channel 1). note: see description for control bit rnoutl for detailed operation. symbol lead no. i/o/p type name/function
temx8 txc-04218 - 23 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 controls, external clock, framing pulses and test leads rnon rvtfn (n=1-8) y13, aa15, w15, y17, ab21, w20, y22, u21 o(t) cmos3v 4ma receive channel n data negative rail, tu/vt framing pulse: when control bits rnlint1/0 are set to 10, negative rail e1/t1 data (rnon) is provided on this lead. when control bits rnlint1/0 are set to 11, a vt/tu framing pulse (rvtfn) is provided on this lead. this lead is disabled when control bits rnlint1/0 are 00. when disabled, this lead can be forced to ether a high impedance state (control bit rnoutl is a 0), or to zeros (control bit rnoutl is a 1). lead y13 is rno1/rvtf1 (channel 1). note: see description for control bit rnoutl for detailed oper- ation. output will be forced low during normal operation while in nrz mode. tcin tclkn tvtcn (n=1-8) aa14, w14, aa17, ab20, y19, aa22, u20, r19 i/o(t) ttl3v/ cmos3v 4ma transmit channel n rail, nrz input clock, vt/tu output clock: a ds1 or e1 clock input when the rail or nrz interface is selected or a vt/tu clock output when the vt/tu interface is selected. tcin is the e1/t1 rail clock (control bits tnlint1/0 (bits 7/6, register x+002h) are 10). tclkn is the e1/t1 nrz clock (control bits tnlint1/0 are 01). tvtcn is the vt/tu nrz clock output (control bits tnlint1/0 are 11). rail (tpin/tnin), nrz (tdatn/tlosn ) or vt/tu nrz data (tvtdn) is clocked in on negative transitions of this clock when control bit tnclki (bit 3, register x+002h) is a 0. when control bit tnclki is a 1, data is clocked in on positive transitions of this clock. lead aa14 is tci1/tclk1/tvtc1 (channel 1). tpin tdatn tvtdn (n=1-8) ab14, ab16, y16, aa18, w18, v19, v21, t20 ittl3v transmit channel n data positive rail, nrz, or vt/tu: when control bits tnlint1/0 are set to 10, positive rail e1/t1 data (tpin) is clocked in this lead. when control bit tnlint1/0 are set to 01, nrz e1/t1 data (tdatn) is clocked in on this lead. when control bits tnlint1/0 are set to 11, vt/tu nrz data (tvtdn) is clocked in on this lead. lead ab14 is tpi1/tdat1/tvtd1 (channel 1). tnln/ tlosn (n=1-8) w13, y15, ab18, w17, aa20, w21, t19, u22 ittl3v transmit channel n data negative rail, external loss of signal, coding violations: when control bits tnlint1/0 are set to 10, negative rail e1/t1 data (tnin) is clocked in on this lead. when control bits tnlint1/0 are set to 01, an external loss of signal (when control bit exnlos (bit 1, register x+003h) is a 1) is clocked in on this lead. when control bit exnlos is a 0, external coding violations can be clocked in on this lead. lead w13 is tni1/tlos1 . symbol lead no. i/o/p type name/function test u3 i ttl3vp transwitch test lead: this lead is used for transwitch testing and must remain an active high for the mapper to function. this lead is pulled high by an internal pull-up to vdd2. it must be left floating or held high. symbol lead no. i/o/p type name/function
temx8 txc-04218 - 24 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 dsclk ab12 i ttl3v desynchronizer reference clock: this clock is used for desynchro- nizer operation and for other internal functions, such as generating a receive ais signal. the clock frequency must be 68.68 mhz (+/- 30 ppm over life) and the clock duty cycle must be (50 +/- 10)%. reset y5 i ttl3vp hardware reset: when an active low pulse is applied to this lead for a minimum duration of 150 nanoseconds after power is applied, this pulse clears all performance counters and alarms, resets the control bits, and initializes the internal fifos. this action takes approximately 4 micro- seconds. status bit resetd (bit 0, register 059h) is set to 1 when the reset is complete. this lead is pulled high by an internal pull-up to vdd2. highz t4 i ttl3vp high impedance select: a low forces all output leads, except the boundary scan lead tdo, to the high impedance state for testing pur- poses. this lead is pulled high by an internal pull-up to vdd2. pm1s u2 i ttl3v one second performance clock input. this clock input is used for the one second shadow counters, and pm (performance monitoring)/fm (fault monitoring) alarm registers. this clock should be a 1.0 hz +/- 32 ppm clock, with a minimum 30 ns high and low time. when this lead is held low, the pm/fm alarm and shadow counter features are disabled. this clock is required to write to the bit leak registers in x+017h and x+018h. abte v1 i ttl3vp add bus timing output signals enable: an active low enables the like-named drop bus clock, c1j1v1 and spe signals to be provided as output signals on the add bus when the drop bus timing mode is selected (lead abust is high). when high, the clock, c1j1v1, and spe signals are disabled as outputs on the add buses when the drop bus timing mode is selected. this lead is pulled high by an internal pull-up to vdd2. vtfa15 t2 o cmos3v 4 ma transmit vt1.5 framing pulse. positive one clock cycle pulse that is used when the vt/tu line interface is selected for a channel. the pulse determines the start of the vt1.5/tu-11 multiframe in the transmit direction for add bus a. the pulse occurs even when no vt/tu line interface is selected (as long as add bus a is active). the pulse is clocked out on the ris- ing edge of the tvtcn clock when control bit tnclki (bit 3, register x+002h) is a 0. vtfa2 r4 o cmos3v 4 ma transmit vt2 framing pulse. positive one clock cycle pulse that is used when the vt/tu line interface is selected for a channel. the pulse deter- mines the start of the vt2/tu-12 multiframe in the transmit direction for add bus a. the pulse occurs even when no vt/tu line interface is selected (as long as add bus a is active). the pulse is clocked out on the rising edge of the tvtcn clock when control bit tnclki (bit 3, register x+002h) is a 0. vtfb15 u1 o cmos3v 4 ma transmit vt1.5 framing pulse. positive one clock cycle pulse that is used when the vt/tu line interface is selected for a channel. the pulse determines the start of the vt1.5/tu-11 multiframe in the transmit direction for add bus b. the pulse occurs even when no vt/tu line interface is selected (as long as add bus b is active). the pulse is clocked out on the ris- ing edge of the tvtcn clock when control bit tnclki (bit 3, register x+002h) is a 0. symbol lead no. i/o/p type name/function
temx8 txc-04218 - 25 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 microprocessor bus interface selection microprocessor bus interface - split bus for motorola (m) or intel (i) vtfb2 t3 o cmos3v 4 ma transmit vt2 framing pulse. positive one clock cycle pulse that is used when the vt/tu line interface is selected for a channel. the pulse deter- mines the start of the vt2/tu-12 multiframes in the transmit direction for add bus b. the pulse occurs even when no vt/tu line interface is selected (as long as add bus b is active). the pulse is clocked out on the rising edge of the tvtcn clock when control bit tnclki (bit 3, register x+002h) is a 0. abust w1 i ttl3vp add bus timing select: a low selects the add bus timing mode. in this timing mode, the drop and add bus timing signals are independent of each other. a high selects the drop bus timing mode. in this timing mode, the add signals (add bus clock, spe and c1j1v1 signals) are derived from the like-named drop bus. note: the add bus timing mode must be selected when any of the chan- nels are assigned to a vt/tu interface. in addition, the j1 and v1 pulses must be fixed regarding their locations. this restriction is required, because the temx8 provides the downstream circuitry with timing infor- mation. this lead is pulled high by an internal pull-up to vdd2. symbol lead no. i/o/p type name/function moto y12 i ttl3v motorola mode : the following table lists the bus selection options. moto a ctio n l intel bus interface h motorola bus interface symbol lead no. i/o/p type name/function a(14-0) ab6, aa7, y8, w9, ab7, aa8, ab8, y9, w10, aa9, ab9, y10, aa10, w11, ab10 i ttl3v address bus (motorola/intel buses): these address line inputs are used for accessing memory map locations for a read/write cycle. a14 (lead ab6) is the most significant bit. d(7-0) aa5, y6, w7, ab4, ab5, aa6, y7, w8 i/o(t) ttl3v/ cmos3v 8ma data bus (motorola/intel buses): bidirectional data lines used for transferring data to or from a memory map location. d7 (lead aa5) is the most significant bit. sel y11 i ttl3v select: an active low enables data transfers between the micropro- cessor and the memory map location during a read/write cycle. symbol lead no. i/o/p type name/function
temx8 txc-04218 - 26 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 boundary scan interface rd / rd/wr aa11 i ttl3v read (i mode) or read/write (m mode): intel mode - an active low signal generated by the microprocessor for reading memory map locations. motorola mode - an active high signal generated by the micropro- cessor for reading the memory map locations. an active low signal is used to write to memory map locations. wr / lds ab11 i ttl3v write (i mode) or device select (m mode): intel mode - an active low signal generated by the microprocessor for writing to memory map locations. motorola mode - the sel and lds inputs are logically or-gated inside the device, generating an internal active low select signal (cs ) that is similar to sel . this internal signal is used to enable data transfer. this lead can be used for the interface with the motorola 68302 microprocessor. if this lead is not used, it should be tied to ground. rdy / dtack ab13 o(t) cmos3v 8ma ready (i mode) or data transfer acknowledge (m mode): intel mode - a high is an acknowledgment from the addressed mem- ory map location that the transfer can be completed. a low indicates that the mapper cannot complete the transfer cycle, and that micro- processor wait states must be generated. motorola mode - during a read bus cycle, a low signal indicates that the information on the data bus is valid. during a write bus cycle, a low signal acknowledges the acceptance of data. int/ irq aa12 o cmos3v 8ma interrupt: a high on this output lead signals an interrupt request int to the microprocessor, as required for intel compatibility micropro- cessors. for motorola operation, a low signals an interrupt request irq to the microprocessor. please note: it will take approximately 4 microseconds before the interrupt is asserted after the last enabling mask bit is set to 1. the interrupt is asserted immediately when the gating event is the latched alarm. symbol lead no. i/o/p type name/function tck aa3 i ttl3v ieee 1149 . 1 test port serial scan clock: this signal is used to shift data into tdi on the rising edge, and out of tdo on the falling edge. the maximum clock frequency is 10 mhz. tms aa2 i ttl3vp ieee 1149.1 test port mode select: tms is sampled on the rising edge of tck, and is used to place the test access port controller into various states as defined in ieee 1149.1. this lead is set high internally by an internal pull-up to vdd2 for normal operation. tdi ab2 i ttl3vp ieee 1149.1 test port serial scan data in: serial test instructions and data are clocked into this lead on the rising edge of tck. this input has an internal pull-up to vdd2. symbol lead no. i/o/p type name/function
temx8 txc-04218 - 27 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 transwitch test leads tdo w5 o(t) cmos3v 4ma ieee 1149.1 test port serial scan data out: serial test instruc- tions and data are clocked out of this lead on the falling edge of tck. when inactive, this 3-state output will be put into its high impedance state. trs y4 i ttl3vp ieee 1149.1 test port reset lead: this lead will asynchronously reset the test access port (tap) controller. this lead must be held low, asserted low or pulsed low (for a minimum duration of 20 ns) to reset the tap controller on temx8 power-up. this input has an inter- nal pull-up to vdd2. failure to perform a tap controller reset may cause the tap controller to take control of some of the temx8 output leads. symbol lead no. i/o/p type name/function testi v2, v3, w3, y1, aa1 i ttl3vd transwitch test input leads: for transwitch testing purposes only. these leads have an internal pull down to gnd and should be held low. testo u4, v4, w2, y2 o(t) cmos3v 4 ma transwitch test output leads: for transwitch testing purposes only. these leads should be left open (floating). symbol lead no. i/o/p type name/function
temx8 txc-04218 - 28 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the ?caution? label on the drypack bag in which devices are supplied. 3. test method for esd per mil-std-883e, method 3015.7. 4. device core is 1.8v only. thermal characteristics power requirements notes: 1. typical values are based on measurements made with nominal voltages at 25 c. maximum values are based on measurements made at maximum voltages at 85 c. 2. all 8 channels are configured as e1 and are being added and dropped in dual protection ring mode. parameter symbol min max unit conditions core supply voltage, +1.8v nominal v dd1 -0.3 2.1 v notes 1, 4 i/o supply voltage, +3.3v nominal v dd2 -0.3 3.9 v notes 1, 4 dc input voltage vin -0.5 5.5 v notes 1, 4 storage temperature range t s -55 150 c note 1 ambient operating temperature t a -40 85 c 0 ft/min. linear airflow moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 2000 v note 3 latch-up lu meets jedec std-78 parameter min typ max unit test conditions thermal resistance - junction to ambient 22 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd2 3.15 3.3 3.45 v i dd2 36 48 ma see notes 1 and 2 p dd2 119 166 mw see notes 1 and 2 v dd1 1.71 1.8 1.89 v i dd1 262 336 ma see notes 1 and 2 p dd1 472 635 mw see notes 1 and 2
temx8 txc-04218 - 29 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 input, output and input/output parameters input parameters for ttl3v (5 volt tolerant) input parameters for ttl3vp (5 volt tolerant, pull-up resistor) input parameters for ttl3vd (5 volt tolerant, pull-down resistor) parameter min typ max unit test conditions v ih 2.3 5.5 v 3.15 < v dd2 < 3.45 v il 1.0 v 3.15 < v dd2 < 3.45 input leakage current 10 na 1 a av dd2 = 3.45 input capacitance 3.1 pf parameter min typ max unit test conditions v ih 2.3 v 3.15 < v dd2 < 3.45 v il 1.0 v 3.15 < v dd2 < 3.45 input current 10 na 1 av i = v dd2 input leakage current 25 100 av dd2 =3.45; input = 0 volts input capacitance 3.1 pf parameter min typ max unit test conditions v ih 2.3 v 3.15 < v dd2 < 3.45 v il 1.0 v 3.15 < v dd2 < 3.45 input current -10 na -1 av i = 0v input leakage current 28 100 av dd2 = 3.45; input = 3.45 volts input capacitance 3.1 pf
temx8 txc-04218 - 30 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 output parameters for cmos3v 4ma output parameters for cmos3v 8ma parameter min typ max unit test conditions v oh 2.4 v v dd2 = 3.15; i oh = -4.0 v ol 0.4 v v dd2 = 3.15; i ol = 4.0 i ol 4.4 8.5 ma v ol =0.4 v i oh -6.4 -20 ma v oh =2.4 v t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf leakage tristate 10 na 1 a 0 to 3 v input output capacitance 3.1 pf parameter min typ max unit test conditions output capacitance 7.5 pf v oh 2.4 v v dd2 = 3.15; i oh = -8.0 v ol 0.4 v v dd2 = 3.15; i ol = 8.0 i ol 8.8 17 ma i oh -12.8 -40 ma t rise t fall leakage tristate 10 na 1 a 0 to 3 v input
temx8 txc-04218 - 31 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 input/output parameters for ttl3vp input and cmos3v output 4ma (5 volt tolerant input) input/output parameters for ttl3v input and cmos3v output 8ma (5 volt tolerant input) note: 1. the leakage current is from v dd2 . it is most pronounced at -40 o c. parameter min typ max unit test conditions v ih 2.3 5.5 v 3.15 < v dd2 < 3.45 v il -0.5 1.0 v 3.15 < v dd2 < 3.45 input leakage current 10 na 1 a 0 to 3.3 v input input capacitance 3.1 pf v oh 2.4 v v dd2 = 3.15; i oh = -4.0 v ol 0.4 v v dd2 = 3.15; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf parameter min typ max unit test conditions v ih 2.3 v 3.15 < v dd2 < 3.45 v il 1.0 v 3.15 < v dd2 < 3.45 input leakage current 10 na 1 a 0 to 3.3 v input; see note 1. input capacitance 3.1 pf v oh 2.4 v v dd2 = 3.15; i oh = -8.0 v ol 0.4 v v dd2 = 3.15; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf
temx8 txc-04218 - 32 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 timing characteristics detailed timing diagrams for the temx8 device are illustrated in the following figures with values of the timing intervals tabulated below the waveform diagrams. the tristate condition of a signal waveform is shown as mid- way between high and low. the timing parameters are measured at voltage levels of (v ih + v il )/2 for input sig- nals or (v oh +v ol )/2 for output signals, unless otherwise indicated. where a waveform diagram describes both a and b bus signals, their symbols are combined in labeling the waveform (e.g., a/badd for aadd and badd ). figure 7. channels 1 - 8 ds1/e1 transmit rail interface timing notes: 1. tcin is shown for tnclki = 0, where data is clocked in on falling edges for channel n. data is clocked in on rising edges when tnclki =1. ds1 interface e1 interface parameter symbol min typ max unit tcin clock period t cyc 580.0 647.7 ns tcin clock low time t pwl 280 ns tcin clock high time t pwh 280 ns tpin/tnin data setup time before tcin t su 15 ns tpin/tnin data hold time after tcin t h 2.0 ns parameter symbol min typ max unit tcin clock period t cyc 435.0 488.28 ns tcin clock low time t pwl 150 ns tcin clock high time t pwh 150 ns tpin/tnin data setup time before tcin t su 15 ns tpin/tnin data hold time after tcin t h 2.0 ns t cyc t pwh t pwl t su t h tcin (input) tpin/tnin (input) note: n = 1 - 8
temx8 txc-04218 - 33 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 8. channels 1 - 8 ds1/e1 transmit nrz interface timing notes: 1. tclkn is shown for tnclki = 0, where data is clocked in on falling edges for channel n. data is clocked in on rising edges when tnclki =1. 2. the negative rail lead may be used to input an external loss of signal indication when control bit exnlos = 1. the loss-of-signal indication must be present for a minimum of 8 tclkn cycles. when control bit exnlos = 0, external coding violations may be clocked in. when control bit exnlosp = 0, the external loss-of-signal. code violations are counted when tlosn is high and the tclkn edge occurs per the tnclki selection (see note 1 above). ds1 interface e1 interface parameter symbol min typ max unit tclkn clock period t cyc 580.0 647.7 ns tclkn clock low time t pwl 280 ns tclkn clock high time t pwh 280 ns tdatn data setup time before tclkn t su(1) 15 ns tdatn data hold time after tclkn t h(1) 2.0 ns tlosn data setup time before tclkn t su(2) 15 ns tlosn data hold time after tclkn t h(2) 2.0 ns parameter symbol min typ max unit tclkn clock period t cyc 435.0 488.28 ns tclkn clock low time t pwl 150 ns tclkn clock high time t pwh 150 ns tdatn data setup time before tclkn t su(1) 15 ns tdatn data hold time after tclkn t h(1) 2.0 ns tlosn data setup time before tclkn t su(2) 15 ns tlosn data hold time after tclkn t h(2) 2.0 ns t cyc t pwh t pwl t su(1) t h(1) tclkn (input) tdatn (input) note: n = 1 - 8 tlosn (input) t h(2) t su(2)
temx8 txc-04218 - 34 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 9. channels 1 - 8 transmit vt/tu interface timing -gapped pointer bytes notes:- tvtcn is shown for tnclki =0, data with falling edge & frame pulse with rising edge. - clock gaps are present during the time of pointer bytes v1-v4. when tnclki = 1, timing is similar to figure 10 . vt 1.5 interface vt 2 interface parameter symbol min typ max unit tvtcn clock period t cyc 565.84 5401.20 ns tvtcn clock low time t pwl 257.20 5144.0 ns tvtcn clock high time t pwh 257.20 5144.0 ns tvtcn clock frequency (nominal) 1.664 mhz tvtdn data setup time before tvtcn t su 30 ns tvtdn data hold time after tvtcn t h 2.0 ns vtfa/b15 delay from tvtcn t d(1) 45 51 ns multiframe time t pw(1) 500 500 s vtfa/b15 pulse width t pw(2) 565.84 875.0 ns parameter symbol min typ max unit tvtcn clock period t cyc 411.52 4166.64 ns tvtcn clock low time t pwl 205.76 3960.88 ns tvtcn clock high time t pwh 205.76 3960.88 ns tvtcn clock frequency (nominal) 2.240 mhz tvtdn data setup time before tvtcn t su 30 ns tvtdn data hold time after tvtcn t h 2.0 ns vtfa/b2 delay from tvtcn t d(1) 45 51 ns multiframe time t pw(1) 500 500 s vtfa/b2 pulse width t pw(2) 462.96 772 ns tvtcn (input) vtfa15 vtfa2 vtfb15 vtfb2 (outputs) tvtdn (output) t pw(1) v1 byte t pwh t pw(2) t d(1) tvtcn (output) t pwl vtfa15 vtfa2 vtfb15 vtfb2 (outputs) (input) tvtdn t h t su note: n = 1 - 8 last bit in multi-frame t cyc
temx8 txc-04218 - 35 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 10. channels 1 - 8 transmit vt/tu interface timing-gapped pointer & poh byte notes: - tvtcn is shown for tnclki = 1, data with rising edge & frame pulse with falling edge. - clock gaps are present during the time of pointer bytes (v1-v4) and the overhead bytes (v5, j2, n2/z6, k4/z7), and may not be contiguous. when tnclki = 0, timing is similar to figure 9 . vt 1.5 interface vt 2 interface parameter symbol min typ max unit tvtcn clock period t cyc 565.84 9927.92 ns tvtcn clock low time t pwl 257.20 9670.72 ns tvtcn clock high time t pwh 257.20 9670.72 ns tvtcn clock frequency (nominal) 1.600 mhz tvtdn data setup time before tvtcn t su 30 ns tvtdn data hold time after tvtcn t h 2.0 ns vtfa/b15 delay from tvtcn t su(2) 45 51 ns multiframe time t pw(1) 500 500 s vtfa/b15 pulse width t pw(2) 565.84 875.0 ns parameter symbol min typ max unit tvtcn clock period t cyc 411.52 7561.68 ns tvtcn clock low time t pwl 205.76 7355.92 ns tvtcn clock high time t pwh 205.76 7355.92 ns tvtcn clock frequency (nominal) 2.176 mhz tvtdn data setup time before tvtcn t su 30 ns tvtdn data hold time after tvtcn t h 2.0 ns vtfa/b2 delay from tvtcn t su(2) 45 51 ns multiframe time t pw(1) 500 500 s vtfa/b2 pulse width t pw(2) 462.96 772 ns tvtcn (input) t cyc t pwh t pw(2) t d(1) tvtcn (output) vtfa15 vtfa2 vtfb15 vtfb2 (outputs) tvtdn (output) t pw(1) t pwl vtfa15 vtfa2 vtfb15 vtfb2 (outputs) (input) tvtdn t h t su v5 & v1 bytes note: n = 1 - 8 last bit in multiframe
temx8 txc-04218 - 36 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 11. channels 1 - 8 ds1/e1 receive rail timing note: rcon is shown for rnclki=0, where data is clocked out on falling edges. data is clocked out on rising edges when rnclki=1. ds1 interface e1 interface parameter symbol min typ max unit rcon clock period t cyc 640 656 ns rcon clock low time t pwl 320 335 ns rcon clock high time t pwh 320 321 ns rpon/rnon data delay after rcon t od -5.0 5.0 ns parameter symbol min typ max unit rcon clock period t cyc 480 498 ns rcon clock low time t pwl 233 248 ns rcon clock high time t pwh 247 248 ns rpon/rnon data delay after rcon t od -5.0 5.0 ns t cyc t pwl t pwh t od rcon (output) rpon/rnon (output) note: n = 1 - 8
temx8 txc-04218 - 37 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 12. channels 1 - 8 ds1/e1 receive nrz timing note: rcon is shown for rnclki=0, where data is clocked out on falling edges. data is clocked out on rising edges when rnclki=1. ds1 interface e1 interface parameter symbol min typ max unit rclkn clock period t cyc 637 658 ns rclkn clock low time t pwl 320 335 ns rclkn clock high time t pwh 318 321 ns rdatn data delay after rclkn t od -5.0 5.0 ns parameter symbol min typ max unit rclkn clock period t cyc 480 498 ns rclkn clock low time t pwl 233 248 ns rclkn clock high time t pwh 247 248 ns rdatn data delay after rclkn t od -5.0 5.0 ns t cyc t pwl t pwh t od rclkn (output) rdatn (output) note: n = 1 - 8
temx8 txc-04218 - 38 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 13. channels 1 - 8 receive vt/tu interface timing -gapped pointer bytes notes: - rvtcn is shown for rnclki = 0, data & frame pulse with falling edge. - clock gaps are present during the time of pointer bytes v1-v4. when rnclki = 1, timing is similar to figure 14 . vt 1.5 interface vt 2 interface parameter symbol min typ max unit rvtcn clock period t cyc 553.3 5080.0 ns rvtcn clock low time t pwl 291.2 4804.0 ns rvtcn clock high time t pwh 262.1 276.6 ns rvtcn clock frequency (nominal) 1.664 mhz rvtfn delay after rvtcn t d(1) 13.1 14.5 ns rvtdn delay after rvtcn t d(2) 14.0 14.5 ns multiframe time t pw(1) 500 500 s rvtfn pulse width t pw(2) 567.8 873 ns parameter symbol min typ max unit rvtcn clock period t cyc 422.2 4000.0 ns rvtcn clock low time t pwl 233.0 3811.0 ns rvtcn clock high time t pwh 189.3 189.3 ns rvtcn clock frequency (nominal) 2.240 mhz rvtfn delay after rvtcn t d(1) 13.1 14.5 ns rvtdn delay after rvtcn t d(2) 14.0 14.5 ns multiframe time t pw(1) 500 500 s rvtfn pulse width t pw(2) 422.2 770 ns rvtcn (output) rvtfn (outputs) rvtdn (output) t pw(1) v1 byte t cyc t pwh t pw(2) t d(1) rvtcn (output) t pwl rvtfn (output) rtvdn (output) t d(2) note: n = 1 - 8 last bit in multiframe
temx8 txc-04218 - 39 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 14. channels 1 - 8 receive vt/tu interface timing-gapped pointer & poh byte notes: - rvtcn is shown for rnclki = 1, data & frame pulse with rising edge. - clock gaps are present during the time of pointer bytes (v1-v4) and the overhead bytes (v5, j2, n2/z6, k4/z7), and may not be contiguous. when rnclki = 0, timing is similar to figure 13 . vt 1.5 interface vt 2 interface parameter symbol min typ max unit rvtcn clock period t cyc 553.3 9930.1 ns rvtcn clock low time t pwl 291.2 9668.0 ns rvtcn clock high time t pwh 262.1 276.6 ns rvtcn clock frequency (nominal) 1.600 mhz rvtfn delay after rvtcn t d(1) 13.1 14.5 ns rvtdn delay after rvtcn t d(2) 14.0 14.5 ns multiframe time t pw(1) 500 500 s rvtfn pulse width t pw(2) 567.8 873 ns parameter symbol min typ max unit rvtcn clock period t cyc 422.2 7425.7 ns rvtcn clock low time t pwl 233.0 7236.4 ns rvtcn clock high time t pwh 189.3 189.3 ns rvtcn clock frequency (nominal) 2.176 mhz rvtfn delay after rvtcn t d(1) 13.1 14.5 ns rvtdn delay after rvtcn t d(2) 14.0 14.5 ns multiframe time t pw(1) 500 500 s rvtfn pulse width t pw(2) 422.2 770 ns rvtcn (output) rvtf15 (outputs) rvtdn (output) t pw(1) v5 & v1 bytes t cyc t pwh t pw(2) t d(1) rvtcn (output) t pwl rvtfn (output) (output) rvtdn t d(2) note: n = 1 - 8 last bit in multiframe (output)
temx8 txc-04218 - 40 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 15. sts-3 a/b drop and add bus signals, timing derived from drop bus (lead abte low) note: a single tu/vt (number 21/28 in sts-1 number 3) is shown for illustration purposes. the a and b add bus outputs are delayed an additional clock cycle from their respective drop bus timing inputs when control bit abod (bit 1, 03bh) is written with a 1. parameter symbol min typ max unit a/bdclk clock period t cyc 51.44 ns a/bdclk duty cycle t pwh /t cyc 40 50 60 % a/bd(7-0)/a/bdpar data /parity setup time before a/bdclk t su(1) 5.0 ns a/bd(7-0)/a/bdpar data /parity hold time after a/bdclk t h(1) 2.0 ns a/bdspe setup time before a/bdclk t su(2) 5.0 ns a/bdspe hold time after a/bdclk t h(2) 3.0 ns a/bdc1j1v1 setup time before a/bdclk t su(3) 5.0 ns a/bdc1j1v1 hold time after a/bdclk t h(3) 3.0 ns a/baclk delay from a/bdclk t od(1) 4.0 12.0 ns a/bac1j1v1 delay from a/baclk t od(2) -2.0 2.5 ns a/baspe delay from a/bclk t od(3) -2.0 2.5 ns a/b(7-0) and a/bapar data /parity out valid delay from a/baclk t od(4) -2.0 10.0 a/badd delay from a/baclk t od(5) -2.0 7.0 ns note: all output times are measured with the 50 pf load capacitance. t h(2) t pwh t su(1) t h(1) c1(1) a/badd (output) a/ba(7-0) (output) a/bdc1j1v1 (input) a/bdspe (input) a/bdclk (input) c1(2) c1(3) data tu/vt selected j1 byte sts-1 #1 sts-1 #2 sts-1 #3 data sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) tu/vt selected occurs every four frames when provided in place of the h4 byte t su(3) t h(3) t cyc t su(2) t od(4) t od(2) t od(5) t od(3) a/bd(7-0) (input) a/bdpar a/bapar a/baclk (output) a/bac1j1v1 (output) c1(1) a/baspe (output) j1 sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 t od(1)
temx8 txc-04218 - 41 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 16. sts-3 a/b drop and add bus signals, timing derived from drop bus (lead abte high) note: a single tu/vt (number 21/28 in sts-1 number 3) is shown for illustration purposes. the a and b add bus outputs are delayed an additional clock cycle from their respective drop bus timing inputs when control bit abod (bit 1, 03bh) is written with a 1. parameter symbol min typ max unit a/bdclk clock period t cyc 51.44 ns a/bdclk duty cycle t pwh /t cyc 40 50 60 % a/bd(7-0)/a/bdpar data /parity setup time before a/bdclk t su(1) 5.0 ns a/bd(7-0)/a/bdpar data /parity hold time after a/bdclk t h(1) 2.0 ns a/bdspe setup time before a/bdclk t su(2) 5.0 ns a/bdspe hold time after a/bdclk t h(2) 3.0 ns a/bdc1j1v1 setup time before a/bdclk t su(3) 5.0 ns a/bdc1j1v1 hold time after a/bdclk t h(3) 3.0 ns a/ba(7-0)/a/bapar data /parity out valid delay from a/bdclk t od(1) 4.0 21.0 ns a/ba(7-0)/a/bapar data /parity to tristate delay from a/bdclk t od(2) 4.0 15.0 ns a/b add add indicator delay from a/bdclk t od(4) 4.0 18.0 ns a/ba(7-0)/a/bapar data /parity out tristate to driven delay from a/bdclk t od(3) 4.0 15.0 ns note: all output times are measured with the 50 pf load capacitance. t h(2) t pwh t su(1) t h(1) c1(1) a/badd (output) a/ba(7-0) (output) a/bdc1j1v1 (input) a/bdspe (input) a/bdclk (input) c1(2) c1(3) data tu/vt selected j1 byte sts-1 #1 sts-1 #2 sts-1 #3 data sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) tu/vt selected occurs every four frames when provided in place of the h4 byte t su(3) t h(3) t cyc t su(2) t od(1) t od(2) t od(4) t od(3) a/bd(7-0) (input) a/bdpar a/bapar
temx8 txc-04218 - 42 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 17. stm-1 vc-4 a/b drop and add bus signals, timing derived from drop bus (lead abte low) note: a single tu/vt (number 21/28 in sts-1 number 3) is shown for illustration purposes. the a and b add bus outputs are delayed an additional clock cycle from their respective drop bus timing inputs when control bit abod (bit 1, 03bh) is written with a 1. parameter symbol min typ max unit a/bdclk clock period t cyc 51.44 ns a/bdclk duty cycle t pwh /t cyc 40 50 60 % a/bd(7-0)/a/bdpar data /parity setup time before a/bdclk t su(1) 5.0 ns a/bd(7-0)/a/bdpar data /parity hold time after a/bdclk t h(1) 2.0 ns a/bdspe setup time before a/bdclk t su(2) 5.0 ns a/bdspe hold time after a/bdclk t h(2) 3.0 ns a/bdc1j1v1 setup time before a/bdclk t su(3) 5.0 ns a/bdc1j1v1 hold time after a/bdclk t h(3) 3.0 ns a/baclk delay from a/bdclk t od(1) 4.0 12.0 ns a/bac1j1v1 delay from a/baclk t od(2) -2.0 2.5 ns a/baspe delay from a/bclk t od(3) -2.0 2.5 ns a/b(7-0) and a/bapar data /parity out valid delay from a/baclk t od(4) -2.0 10.0 a/badd delay from a/baclk t od(5) -2.0 7.0 ns note: all output times are measured with the 50 pf load capacitance. t h(2) t pwh t su(1) t h(1) c1(1) a/badd (output) a/ba(7-0) (output) a/bdc1j1v1 (input) a/bdspe (input) a/bdclk (input) c1(2) c1(3) data tu/vt selected j1 byte sts-1 #1 sts-1 #2 sts-1 #3 data sts-1 #1 j1 c1(1) tu/vt selected t su(3) t h(3) t cyc t su(2) t od(4) t od(2) t od(5) t od(3) a/bd(7-0) (input) a/bdpar a/bapar a/baclk (output) a/bac1j1v1 (output) c1(1) a/baspe (output) j1 t od(1) occurs every four frames when provided in place of the h4 byte
temx8 txc-04218 - 43 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 18. stm-1 vc-4 a/b drop and add bus signals, timing derived from drop bus (lead abte high) note: a single tu/vt (number 21/28 in sts-1 number 3) is shown for illustration purposes. the a and b add bus outputs are delayed an additional clock cycle from their respective drop bus timing inputs when control bit abod (bit 1, 03bh) is written with a 1. parameter symbol min typ max unit a/bdclk clock period t cyc 51.44 ns a/bdclk duty cycle t pwh /t cyc 40 50 60 % a/bd(7-0)/a/bdpar data /parity setup time before a/bdclk t su(1) 5.0 ns a/bd(7-0)/a/bdpar data /parity hold time after a/bdclk t h(1) 2.0 ns a/bdspe setup time before a/bdclk t su(2) 5.0 ns a/bdspe hold time after a/bdclk t h(2) 3.0 ns a/bdc1j1v1 setup time before a/bdclk t su(3) 5.0 ns a/bdc1j1v1 hold time after a/bdclk t h(3) 3.0 ns a/ba(7-0)/a/bapar data /parity out valid delay from a/bdclk t od(1) 4.0 21.0 ns a/ba(7-0)/a/bapar data /parity to tristate delay from a/bdclk t od(2) 4.0 15 ns a/b add add indicator delay from a/bdclk t od(4) 4.0 18.0 ns a/ba(7-0)/a/bapar data /parity out tristate to driven delay from a/bdclk t od(3) 4.0 15.0 ns note: all output times are measured with the 50 pf load capacitance. t h(2) t pwh t su(1) t h(1) c1(1) a/badd (output) a/ba(7-0) (output) a /bdc1j1v1 (input) a/bdspe (input) a/bdclk (input) c1(2) c1(3) data tu/vt selected j1 byte vc-4 j1 c1(1) tu/vt selected occurs every four frames when provided in place of the h4 byte t su(3) t h(3) t cyc t su(2) t od(1) t od(2) t od(4) t od(3) a/bd(7-0) (input) a/bdpar a/bapar
temx8 txc-04218 - 44 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 19. sts-3 a/b add bus signals, timing derived from add bus note: a single tu/vt (number 21/28 in sts-1 number 3) is shown for illustration purposes. the a and b add bus outputs are delayed an additional clock cycle from their respective add bus timing inputs when control bit abod (bit 1, 03bh) is written with a 1. parameter symbol load min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc 40 50 60 % ac1j1v1 setup time before aclk t su(1) 5.0 ns ac1j1v1 hold time after aclk t h(1) 5.0 ns aspe setup time before aclk t su(2) 5.0 ns aspe hold time after aclk t h(2) 5.0 ns a(7-0)/apar data /parity out valid delay from aclk t od(2) 50pf 4.0 21.0 ns a(7-0)/apar data /parity to tristate delay from aclk t od(3) 4.0 15 ns add add indicator delayed from aclk t od(1) 50pf 4.0 17.0 ns a(7-0)/apar data /parity out tristate to driven delay from aclk t od(4) 50pf 4.0 15 ns note: all output times are measured with the specified load capacitance. t h(2) t pwh a/badd (output) a/ba(7-0) (output) a/bac1j1v1 (input) a/baspe (input) a/baclk (input) j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) tu/vt selected occurs every four frames when enabled t su(1) t h(1) t cyc t su(2) t od(2) t od(3) t od(1) v1 sts-1 #2 v1 sts-1 #3 t od(4) a/bapar
temx8 txc-04218 - 45 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 20. stm-1 vc-4 a/b add bus signals, timing derived from add bus note: a single tu/vt (number 21/28 in sts-1 number 3) is shown for illustration purposes. the a and b add bus outputs are delayed an additional clock cycle from their respective add bus timing inputs when control bit abod (bit 1, 03bh) is written with a 1. parameter symbol load min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc 40 50 60 % ac1j1v1 setup time before aclk t su(1) 5.0 ns ac1j1v1 hold time after aclk t h(1) 5.0 ns aspe setup time before aclk t su(2) 5.0 ns aspe hold time after aclk t h(2) 5.0 ns a(7-0)/apar data /parity out valid delay from aclk t od(2) 50pf 4.0 21 ns a(7-0)/apar data /parity to tristate delay from aclk t od(3) 4.0 15 ns add add indicator delayed from aclk t od(1) 50pf 4.0 17 ns a(7-0)/apar data /parity out tristate to driven delay from aclk t od(4) 50pf 4.0 15 ns note: all output times are measured with the specified load capacitance. t h(2) t pwh a/badd (output) a/ba(7-0) (output) a/bac1j1v1 (input) a/baspe (input) a/baclk (input) v1 j1 c1(1) tu/vt selected occurs every four frames when enabled t su(1) t h(1) t cyc t su(2) t od(2) t od(3) t od(1) t od(4) a/bapar
temx8 txc-04218 - 46 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 21. microprocessor read cycle timing - intel note: all output times are measured with a maximum 25 pf load capacitance. parameter symbol min typ max unit a(14-0) address setup time to sel t su(1) 3.0 ns a(14-0) address hold time after rd t h(1) 3.0 ns d(7-0) data output float time after rd t f(1) 15 ns sel setup time to rd t su(2) 3.0 ns rd pulse width t pw(1) 20 ns sel hold time after rd t h(2) 3.0 ns rdy delay after sel t d(2) 8.0 15.0 ns rdy delay after rd t d(3) 14.0 ns rdy float time after sel t f(2) 12.0 ns rdy pulse width t pw(2) 1.2 s data output valid delay after rd t d(1) 12.0 ns data output valid delay after rdy t d(4) 5.0 ns data output tristate to driven delay after rd t d(5) 9.0 ns t su(1) a(14-0) d(7-0) sel rd rdy t su(2) t pw(1) t pw(2) t d(3) t d(2) t f(2) t h(2) t d(1) t f(1) t h(1) (input) (output) (input) (input) (output) t d(4) t d(5) address data
temx8 txc-04218 - 47 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 22. microprocessor write cycle timing - intel note: all output times are measured with a maximum 25 pf load capacitance. parameter symbol min typ max unit a(14-0) address setup time to sel t su(1) 3.0 ns a(14-0) address hold time after wr t h(1) 7ns d(7-0) data input valid setup time to wr t su(2) 5ns d(7-0) data input hold time after wr t h(2) 7ns sel setup time to wr t su(3) 3ns wr pulse width t pw(1) 20 ns rdy delay after sel t d(1) 815ns rdy delay after wr t d(2) 14 ns rdy float time after sel t f 12 ns rdy pulse width t pw(2) 1.2 s d(7-0) data valid setup time to wr t su(4) 3ns t su(1) a(14-0) d(7-0) sel wr rdy t su(4) t su(2) t pw(2) t f t h(2) t h(1) t pw(1) t d(2) t d(1) t su(3) (input) (input) (input) (input) (output) address data
temx8 txc-04218 - 48 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 23. microprocessor read cycle timing - motorola notes: 1. all output times are measured with a maximum 25 pf load capacitance. 2. measured with respect to the later of sel or wr /lds falling edge. 3. measured with respect to the earlier of sel or wr /lds rising edge. parameter symbol min typ max unit a(14-0) address setup time and rd/wr setup time before sel , wr /lds (see note 2) t su(1) 3.0 ns a(14-0) address hold time and rd/wr delay time after sel , wr /lds (see note 3) t h(1) 3ns d(7-0) data output float time after sel , wr /lds (see note 3) t f(1) 15 ns sel or wr /lds pulse width t pw(1) 20 ns dtack driven delay after sel , wr /lds (see note 2) t d(2) 715ns dtack float time after sel , wr /lds (see note 3) t f(2) 12 ns dtack delay after sel , wr /lds (see note 2) t d(6) 1.2 s d(7-0) data output delay after sel , wr /lds (see note 2) t d(1) 1.2 s d(7-0) data output delay after dtack t d(4) 5ns d(7-0) data output tristate to drive delay after sel , wr /lds (see note 2) t d(5) 410ns t su(1) t pw(1) t f(1) t d(6) t h(1) t d(1) t d(2) a(14-0) d(7-0) sel rd/wr dtack wr /lds (input) (input) (output) (input) (output) t d(4) t d(5) address data t f(2) (input)
temx8 txc-04218 - 49 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 24. microprocessor write cycle timing - motorola notes: 1. all output times are measured with a maximum 25 pf load capacitance. 2. measured with respect to the later of sel or wr /lds falling edge. 3. measured with respect to the earlier of sel or wr /lds rising edge. parameter symbol min typ max unit a(14-0) address setup time and rd/wr setup time before sel , wr /lds (see note 2) t su(1) 3ns a(14-0) address hold time and rd/wr delay time after sel , wr /lds (see note 3) t h(1) 8ns d(7-0) data input setup time before sel , wr /lds (see note 3) t su(2) 8ns d(7-0) data input hold time after sel , wr /lds (see note 3) t h(2) 8ns sel or wr /lds pulse width t pw(1) 20 ns dtack driven delay after sel , wr /lds (see note 2) t d(2) 15 ns dtack float time after sel , wr /lds (see note 3) t f 15 ns dtack delay after sel , wr /lds (see note 2) t d(4) 1.2 us t su(1) t pw(1) t h(1) a(14-0) d(7-0) sel rd/wr dtack t su(2) t h(2) (input) (input) (input) (input) (output) address data wr /lds (input) t d(4) t d(2) t f
temx8 txc-04218 - 50 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 25. boundary scan timing note: the output time (tdo) is measured with a maximum of 25 pf load capacitance. parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time before tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time before tck t su(2) 3.0 - ns tdi hold time after tck t h(2) 4.0 - ns tdo delay from tck (see note) t d -25ns trs pulse width t pw(1) 20 - ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl t pw(1) t pw(1) trs (input)
temx8 txc-04218 - 51 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 operation the following sections detail the operation of the temx8 mapper. bus interface modes each channel in the temx8 mapper supports the following sonet/sdh bus modes of operation: - drop mode - add mode - single unidirectional ring mode - multiplexer mode - dual unidirectional ring mode drop mode in the drop mode of operation, tu/vts from both the a and b buses are monitored, and a tu/vt is terminated from either the a or b drop bus to the receive output, without a return path in the transmit direction to the a and b add buses. add mode in the add mode of operation, tu/vts are monitored from the a or b drop buses without a receive output, but a path in the transmit direction for either a or b add buses is provided. single unidirectional ring mode in the single unidirectional ring mode of operation, a tu/vt is dropped from the a (or b) drop bus, with the return path the a (or b) add bus. the other drop bus monitors the vt/tu. timing for the tu/vt to be added to the a (or b) add bus is derived from either the a (or b) drop bus, or from the a (or b) add bus. multiplexer mode in the multiplexer mode of operation, a tu/vt is dropped from the a (or b) drop bus, with the return path the b (or a) add bus. the other drop bus monitors the vt/tu. timing for the tu/vt to be added to the a (or b) add bus is derived from either the a (or b) drop bus, or from the a (or b) add bus. dual unidirectional ring mode in the dual unidirectional ring mode of operation, a tu/vt is dropped from the a (or b) drop bus, with the return path both the a and b add buses. the other drop bus monitors the vt/tu. timing for the tu/vt to be added to the a (or b) add bus is derived from either the a (or b) drop bus, or from the a (or b) add bus.
temx8 txc-04218 - 52 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 bus mode selection the tu/vt bus mode selection is performed by the control bits defined in the table shown below. the n repre- sents the channel number (1-8). note: both the a and b add buses upon power up and reset are in the high impedance state. a 0 must be written to control bits aahze (bit 1, 03ah) and bahze (bit 2, 03ah) for normal add bus operation. bus mode selection for channel n sdh/sonet add/drop multiplexing format selections the control bit settings for the sonet/sdh mapping format selection are given in the table shown below. this selection is valid for both the a and b drop and add buses. a drop bus reset operation should be performed after modifying the sts-3 bit. see dreset bit at address 039h in the memory map description. sts-3 sts-1/stm-1 vc-4 format selection mode type tnsel1 (bit 1, x+006h) tnsel0 (bit 0, x+006h) rnsel (bit 2, x+006h) drop from bus add to bus dropping only, from a 0 0 0 a drop-only (1) dropping only, from b 0 0 1 b drop-only (1) single unidirectional ring 2 010 a a single unidirectional ring 2 011 b b multiplexer, a in, b out 1 0 0 a b multiplexer, b in, a out 1 0 1 b a dual unidirectional ring 1 1 0 a a and b dual unidirectional ring 1 1 1 b b and a notes: 1. when the drop-only mode is selected, the ability to add a tu/vt is disabled, and the add bus is tristated. 2. writing a 1 to control bit fnrdis (bit 3, x+006h) causes the rei value to always be transmitted as zero. in addi- tion, receive side alarms are disabled from generating rdi and rdi is transmitted as zero. however, the micro- processor can send an rdi, if required. format sts3 (bit 1, 01ah) sts-3 format or stm-1 au-3 format 1 stm-1 vc4 format 0
temx8 txc-04218 - 53 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 drop and add tu/vt selection there are four vt/tu selection registers per channel. two registers are used for selecting the vt1.5/tu-11 or vt2/tu-12 (vt2) for the a and b drop buses, and the other two registers are used for selecting the vt1.5/tu-11 or vt2/tu-12 (vt2) for the a and b add buses. thus, two different vt/tus can be assigned to the a and b drop buses, and two different vt/tus can be assigned to the a and b add buses for channel n. in addition, broadcast capability is supported in the drop direction. this feature permits the same vt/tu to be dropped to more than one channel. in the add direction only one channel can be used for the broadcast mode. each selection register consists of eight bits, which is programmed according to the following table. a 00h forces a high impedance state at the receive interface for channel n. in addition, the rei and rdi states will be transmitted as zeros. any unlatched drop bus channel alarms that are set in a channel will remain set when 00 is written into that channel?s drop vt selection register regardless of a change in the alarm condition. in the add direction, a 00h or invalid value forces a high impedance state for that channel. the register assignment for the a side drop bus is: x+012h, a side add bus is: x+01ah, b side drop bus is: x+082h, and the b add bus is: x+08ahb, where x is the channel number (1 to 8) in hex. when changing the value of an add bus per channel vt selection register, 00h should be written into the register first, followed by the new channel assign- ment value. when changing the value of a drop bus per channel vt selection register, 00h should be written into the register, followed by the new channel assignment value. if another channel has been assigned the same value, then nothing else needs to be done. if no other channel has been assigned the same value, then a drop bus a or b per channel reset (control bit dachnr or dbchnr) operation should be performed for the channel whose vt selection register has been modified. a and b drop and add vt/tu selection 76543210 tu/vt type au-3/tug-3 or sts-1 tu/vt group number tu/vt number meaning 00000000 no tu/vt selected 0 vt1.5/tu-11 format 1 vt2/tu-12 format 0 0 not used 0 1 au-3/tug-3 a, sts-1 #1 1 0 au-3/tug-3 b, sts-1 #2 1 1 au-3/tug-3 c, sts-1 #3 0 0 1 tu/vt group number 1 0 1 0 tu/vt group number 2 0 1 1 tu/vt group number 3 1 0 0 tu/vt group number 4 1 0 1 tu/vt group number 5 1 1 0 tu/vt group number 6 1 1 1 tu/vt group number 7 0 1 tu/vt number 1 1 0 tu/vt number 2 1 1 tu/vt number 3 0 0 tu/vt number 4 (vt1.5/tu-11 format)
temx8 txc-04218 - 54 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 bus timing timing for adding a tu/vt to the add bus is derived from the like-named drop bus, or from the like-named add bus. the add bus timing-source selection is determined by lead abust , as shown in the table below. for the drop bus timing mode, the add bus timing is derived from the drop bus clock, c1j1(v1), and spe signals. the v1 pulse may be present in the c1j signal or may be derived from internal h4 multiframe detectors. an option is also provided in which the internal clock, c1j1v1, and spe signals may be provided as outputs on the a and b add buses in the drop bus timing mode. for add bus timing, an input clock, c1j1v1, and spe signal must be provided as input signals. bus timing selection performance counters there are three types of performance counters provided: saturating/rollover, current one second, and previous one-second counters. all counters, other than the one-second counters, can be configured as saturating (when control bit crov (bit 0, 01ah) is a 0), or rollover (when control bit crov is a 1). when a counter is configured to be saturating, it stops at its maximum count. a rollover counter rolls over to zero after maximum count is reached. a saturating counter is reset to 0 by a hardware reset (reset lead), the software reset (reseth control bit), when it is read by the microprocessor, or by any of the following resets as they apply: resetc (resets all per- formance counters), dreset (resets all drop side performance counters), dachnr/dbchnr (resets all a/b drop side performance counters for a selected channel), treset (resets all add side performance counters), and tnreset (resets all add side performance counters for a selected channel). a rollover counter is reset to fffeh/feh by a software reset. a hardware reset sets the crov bit to 0 (satu- rating) and all performance counters to 0. rollover counters do not reset when read by the microprocessor. the software resets must be held high for a minimum of one dsclk clock cycle (excluding reseth which is self clearing). since these resets are not self-clearing they must be brought low before another reset operation can take place. reset action of the current one-second and previous one-second counters is not dependent upon the crov control bit. these counters always reset to 0 (never fffeh/feh) by a hardware or software reset. for a 16-bit counter, the low order byte must be read first, followed by a read of the high order byte, before any other low order byte is read. during a microprocessor read cycle of any performance counter, counts are held and updated afterwards to ensure that no counts are lost. alarm structure all alarm indications are reported as unlatched and latched status bits. the latched bit of an alarm can be set on the positive transitions, negative transitions, or both positive and negative transitions. reading a latched alarm bit clears the bit to 0. control bits intr1 and intr0 (bits 7 and 6, 01bh) should be programmed to select the transition(s) on which the latched bits are set (see table below). abust lead action low add bus timing selected. high drop bus timing selected. intr1 (bit 7, 01bh) intr0 (bit 6, 01bh) action on an alarm 0 0 not used. no latched alarm event indication, or interrupt indication. 1 0 alarm sets latched alarm on positive transitions of the alarm. 0 1 alarm sets latched alarm on negative transitions of the alarm. 1 1 alarm sets latched alarm on positive or negative transitions of the alarm.
temx8 txc-04218 - 55 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 the alarm bits latch according to the various states shown in figure 26 below. figure 26. alarm latching configurations as shown in the above diagram there are three possible alarm latching configurations: positive transition, neg- ative transition, or positive/negative transition. the positive level latching configuration is not supported in this device. for example, assume that control bits intr1 and intr0 are equal to 10. this configures the latched alarm circuits to set on positive transitions (0 to 1) of an alarm. the positive transition of an alarm causes the corresponding latched bit to set to 1. the latched bit will remain set until the register containing the latched bit position is read by the microprocessor, at which time the latched bit positions in the register will be reset to 0. even though the alarm (unlatched) remains active, it will not cause a latched state to recur. the latched bit will remain reset to 0 until another positive alarm (unlatched) transition occurs to set it to 1. one second (shadow) registers the temx8 also provides one second registers for the alarms. the one second register feature in the temx8 is enabled by applying a positive pulse at one-second intervals to lead pm1s. figure 27 illustrates the opera- tion of the one second (shadow) registers for any alarm. this figure assumes that interrupt control bits intr1 and intr0 (bits 7 and 6, 01bh) are set to a value of 11. the one second (pm) status bit is a 1 whenever there is an alarm transition during the last one-second interval or the alarm is present at the end of the last one-sec- ond interval. the persistent (fm) status bit is a 1 if the alarm is active but did not become active during the pre- vious one-second interval. alarm bit (unlatched) alarm bit (unlatched) alarm bit (unlatched) latched bit positive transition intr1, intr0=10 negative transition intr1, intr0=01 positive/negative transition intr1, intr0=11 set on pos. transition clear on read set on neg. transition clear on read set on transition clear on read latched bit latched bit
temx8 txc-04218 - 56 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 27. one second (shadow) register operation interrupt structure the interrupt indication structure contains both global alarm indication and polling registers, along with mask bits at various levels in the interrupt structure. the following figures illustrate the interrupt structure. as shown in figure 30 , the hardware interrupt is controlled by control bit hint (bit 7, 005h). when this control bit is writ- ten with a 0, the hardware interrupt to the microprocessor is disabled. when written with a 1, the hardware interrupt lead is enabled. status bits gda, gdb, gab, pcda, pcdb, and pcab (050h) are global status bits, and will set provided their corresponding mask bits are set to 1 (mgda, mgdb, mga, mpcda, mpcdb, and mpcab (005h)), and the mask bits that correspond to the alarms are also set to 1. status bit gda (bit 5 - 050h) is set to 1 when an alarm occurs on the a drop bus (e.g., loss of b bus clock). status bit gdb (bit 4 - 050h) is set to 1 when an alarm occurs on the b drop bus (e.g., loss of b bus clock). status bit gab (bit 3 - 050h) is set to 1 when an alarm occurs on either of the two add buses (e.g., loss of clock). status bit pcda (bit 2 - 050h) is set to 1 when an alarm occurs in one the 8 channels that is dropping a vt/tu from the a drop bus (e.g., channel 1 has detected a loss of pointer alarm). status bit pcdb (bit 1 - 050h) is set to 1 when an alarm occurs in one the 8 channels that is dropping a vt/tu from the b drop bus (e.g., channel 1 has detected a loss of pointer alarm). status bit pcab (bit 0 - 050h) is set to 1 when an alarm occurs in one the 8 channels that is adding a vt/tu from the a and/or b add bus (e.g., channel 7 has detected a transmit loss of signal alarm). as shown in figure 29 , for each channel there are polling bits (1 through 8) for the a drop side, b drop side, and the add side, with each bit setting to 1, when there is a corresponding alarm, and the mask bits that corre- spond to the polling bit and the alarms are also set to 1. a polling bit in the add polling register (055h) sets to 1 when a channel detects an add side alarm (e.g., channel 3 detects a transmit loss of clock). a polling bit in the a drop polling register (074h) sets to 1 when a channel detects a a drop side alarm for the vt/tu selected (e.g., channel 5 detects a signal label mismatch alarm). a polling bit in the b drop polling registers (094h) sets to 1 when a channel detects a b drop side alarm for the vt/tu selected (e.g., channel 8 detects a unequipped alarm). associated with each one the three polling bits per channel are corresponding mask bits when set to 1, t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec t=7 sec note 1: for this example, latched events are set only on positive and negative event transitions. pm1s unlatched alarm latched alarm (pm) alarm (fm) alarm t=8 sec one second one second
temx8 txc-04218 - 57 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 enable the global polling indication bits. also shown in figure 29 are the drop and add bus alarm locations and their corresponding mask bits for setting the three global bus indication bits. for example, if an upstream ais indication is detected in a drop bus for sts-3 sts-1 no. 1, and the corresponding mask bit is set, a global indi- cation is also set. as shown in figure 28 , each of the alarms has a corresponding mask bit in each channel. these correspond to the add side alarms (e.g., line ais detected), a drop vt/tu alarms (e.g., ndf alarm detected), and b drop vt/tu alarms (e.g., lop alarm detected). when the corresponding mask bit is set to 1, the alarm sets a bit in one of the three polling registers corresponding to the channel. in addition, there is a set of mask bits which can inhibit an alarm type from setting one or more channel bits in a polling register. for example, an unequipped alarm that occurs in any channel can be masked from setting that channels polling bit register location. the interrupt is cleared by reading the latched alarm bit position, or by setting the appropriate mask bits to 0. please note: it will take approximately 4 microseconds before the interrupt will change states when an alarm mask bit is enabled (turned off). figure 28. channel polling alarms mask bits channel n channel n n alarms channel n n alarms bit and bit and bit and channel n n alarms (x+114h to x117h) mask bits a drop alarms (x+013h to x+016h) channel n (x+194h to x+197h) a drop latched alarms b drop latched alarms mask bits b drop alarms (x+083h to x+086h) (x+005h) mask bits add alarms add latched alarms (x+101h) n alarms mask bits per alarm type (007h to 00ah) channel n polling a drop alarms (74h) channel n b drop alarms (094h) channel n polling add alarms (055h) channel n polling channel n channel n mask bits n alarms mask bits n alarms channel n
temx8 txc-04218 - 58 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 29. global indication alarms add alarms channel n polling mask bits add alarms channel n polling channel n polling mask bits a drop alarms a drop alarms channel n polling mask bits b drop alarms b drop alarms bit and n = 1-8 n = 1-8 bit and n = 1-8 n = 1-8 bit and n = 1-8 n = 1-8 global indication add alarms b drop alarms or n = 1 n = 8 channel polling global indication or n = 1 n = 8 channel polling a drop alarms global indication or n = 1 n = 8 channel polling channel n polling (03fh) (074h) (045h) (094h) (04bh) (pcda, bit 2 - 050h) (pcab, bit 0 - 050h) (pcdb, bit 1 - 050h) (055h) bit and a drop bus latched alarms mask bits a drop bus (043h - 044h) (062h - 0063h) b drop bus latched alarms mask bits b drop bus (049h - 04ah) (082h - 083h) add bus latched alarms mask bits a drop bus (03dh) (052h) global indication a drop bus alarms (gda, bit 5 - 50h) bit and global indication b drop bus alarms (gdb, bit 4 - 50h) bit and global indication add bus alarms (gab, bit 3 - 50h) alarms alarms mask bits mask bits mask bits alarms channel n polling
temx8 txc-04218 - 59 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 30. hardware interrupt indication global indication global indication channel polling global indication global indication global indication b drop alarms a drop alarms channel polling channel polling add alarms mask bit mask bit mask bit mask bit mask bit and and and and and and global indication mask bit or control bit hint=1 and hardware interrupt indication add bus alarms a drop bus alarms b drop bus alarms (pcab, bit 0 - 050h) (pcda, bit 2 - 050h) (pcdb, bit 1 - 050h) (gda, bit 5 - 050h) (gdb bit, bit 4 - 050h) (gab, bit 3 - 050h) (bit 7 - 005h) (mgab, bit 3 - 005h) (mgdb, bit 4 - 005h) (mgda, bit 5 - 005h) (mpcdb, bit 1 - 005h) (mpcda, bit 2 - 005h) (mpcab, bit 0 - 005h)
temx8 txc-04218 - 60 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 drop bus interface two sonet/sdh drop buses are provided, and are labeled a side drop, and b side drop. the two drop buses consist of the following leads: input data (a/bd(7-0)), input parity, (a/bdpar), input c1, j1, and optional v1 marker pulses (a/bdc1j1v1), input payload indication (a/bdspe). the most significant bit (msb) is assigned to ad7 and bd7 in the ad(7-0) and bd(7-0) signals. the msb is defined as the first bit received in a sonet/sdh byte (i.e., bit 1 in the sonet/sdh byte). the bus rate is 19.44 kbit/s for sts-3 and stm-1 operation. the sts-1 rate is not supported. the two drop buses are moni- tored for loss of clock. the alarms are adloc (bit 0, 060h) for the a side drop bus and bdloc (bit 0, 080h) for the b side. drop bus parity selection the parity selection for two drop buses, a and b drop, is according to the following table. a parity error for the a side drop bus is indicated by alarm adpar (bit 1, 060h), and for the b side drop bus is indicated by alarm bdpar (bit 1, 080h). other than an alarm indication, no action is taken within the temx8. dbpe (bit 0, 019h) pddo (bit 1, 019h) drop bus parity selection 0 0 odd parity is calculated for the input leads consisting of data (a/bd(7-0)), clock (a/bdclk), c1, j1, and v1 marker pulses (a/bdc1j1v1), and the payload indica- tion (a/bdspe). 0 1 odd parity is calculated for the data input leads (a/bd(7-0)). 1 0 even parity is calculated for the input leads consisting of data (a/bd(7-0)), clock (a/bdclk), c1, j1, and v1 marker pulses (a/bdc1j1v1), and the payload indica- tion (a/bdspe). 1 1 even parity is calculated for the data input leads (a/bd(7-0)).
temx8 txc-04218 - 61 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 drop bus multiframe alignment pointer byte alignment (v1 and v2 bytes) for the vt/tus in the receive direction (from the drop bus) is estab- lished by detecting the multiframe pattern in the h4 byte or the v1 reference pulse in the adc1j1v1 and bdc1j1v1 signal. depending on the format, one or three v1 pulses will be present in this signal. when the h4 byte is used to establish v1 byte alignment, the v1 pulse does not have to be present in the adc1j1v1 or bdc1j1v1 signal. writing a 1 to control bit dv1sel (bit 2, 019h) selects the v1 pulse in the adc1j1v1 and bdc1j1v1 signal to be used to establish the v1 byte location reference, while a 0 selects the h4 byte as the multiframe detector for establishing the v1 reference. the h4 multiframe detection circuits are disabled when the v1 pulse is selected in place of the h4 byte. a drop bus reset operation should be performed after modi- fying the dv1sel bit. see dreset bit at address 039 in the memory map description. for stm-1 vc-4 operation, a single v1 pulse must occur three drop bus clock cycles every four frames follow- ing the j1 pulse. for stm-1 au3/sts-3 operation, three v1 pulses must be present every four frames. each v1 pulse must be present for one clock cycle, three clock cycles after the corresponding j1 pulse, when the spe signal is high. for example, in a vc-4 signal, the j1 pulse identifies the j1 byte location (defined as the starting location for the vc-4) in the poh bytes. in the next column (first clock cycle) all the rows are assigned as fixed stuff. similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. the next column (third clock cycle) defines the start of tug-3 a. this column is where the v1 pulse occurs every four frames. however, the actual v1 byte occurs six clock cycles after the v1 pulse. for sts-1 operation, one v1 pulse must be present. the v1 pulse must occur on the next clock cycle after j1, and when the spe signal is high. the j1 pulse identifies the j1 byte location (defined as the starting location for the sts-1) in the poh bytes. the next column (first clock cycle) defines the vts starting location. thus, the v1 pulse identifies the starting location of the first v1 byte in the signal. the rest of the v1 bytes for the 21 vt2s are also aligned with respect to the v1 pulse. the timing relationships between j1, v1, and other signals are shown in the timing characteristics section. the h4 byte is used to identify the location of the v1 byte as shown in figure 31 below: figure 31. h4 byte floating vt mode bit allocation the h4 byte is monitored for multiframe alignment when enabled. for stm-1 operation, there is only one h4 detector per a and b drop buses. for sts-3 operation, there are three h4 byte detectors, one for each sts-1 for the a side and for the b side drop buses. each sts-1 may have its own phase regarding the h4 multiframe sequence. v1 35 bytes v2 35 bytes v3 35 bytes v4 35 bytes tu-12/vt2 h4 (xxxx xx00) of previous spe h4 (xxxx xx01) h4 (xxxx xx10) h4 (xxxx xx11) v1 26 bytes v2 26 bytes v3 26 bytes v4 26 bytes h4 (xxxx xx00) of previous spe h4 (xxxx xx01) h4 (xxxx xx10) h4 (xxxx xx11) tu-11/vt1.5
temx8 txc-04218 - 62 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 when the h4 multiframe detector is enabled, an out-of-multiframe alarm (axhoom and bxhoom) is declared when an error is detected in bits 7 and 8 of the h4 byte (where x is 1, 2, or 3 for each of the sts-1 signals in an sts-3 or 1 for the stm-1 vc-4 format). recovery occurs when an error free h4 byte sequence is detected in four consecutive frames (beginning with the detection of the 00 code). once in the oom state, if recovery does not take place within 1 ms, an out-of-multiframe alarm (axhlom and bxhlom) is declared (where x is 1, 2, or 3 for each of the sts-1 signals in an sts-3 or 1 for the stm-1 vc-4 format). recovery occurs upon recovering of the axhoom or bxhoom alarm. sdh/sonet ais detection the temx8 can detect an upstream sonet/sdh ais condition using either the h1/h2 pointer bytes or the e1 order wire byte. the selection is according to the following table. note: vt/tu ais is detected by each of the pointer tracking state machines independently of the sonet/sdh h1/h2 or e1 byte ais detection circuitry. when the control bit sts3 (bit1, 01ah) selects the vc-4/tug-3 format, the h1 and h2 bytes or the e1 byte per a and b drop buses are monitored for ais. when the sts3 control bit selects the sts-3 or au-3 format, each set of the three h1/h2 bytes or the e1n bytes per a drop and b drop buses are monitored for an ais indi- cation. each of the three h1/h2 pointer bytes or e1n bytes corresponds to the like-numbered au-3/sts-1 sig- nal (n=1-3). when the h1/h2 bytes are selected and if all ones are detected in the h1/h2 bytes in the a drop bus for three consecutive frames, the alarm bits axuais will set, where x is equal to 1, 2, or 3, which corresponds to the like numbered sts-1. for a vc-4 format, x is equal to 1 only. if all ones are detected in the h1/h2 bytes in the b drop bus for three consecutive frames, the alarm bits bxuais will set. recovery occurs when a normal ndf (bits 1 through 4) in h1 is detected for three consecutive frames. when the e1n bytes are monitored for an upstream ais condition majority logic is used to determine if an e1n byte is carrying an upstream ais indication. if five or more ones are detected in an a/b drop bus e1n byte, the alarm bit axuais or bxuais is set. recovery occurs when four or less ones are detected in the byte. heaise (bit 0, 01dh) se1ais (bit 1, 01dh) action 0 x no upstream ais monitoring performed. 1 0 the h1/h2 bytes are monitored for upstream ais. 1 1 the e1 byte is monitored for upstream ais.
temx8 txc-04218 - 63 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 tu/vt pointer tracking the starting location of the v1 byte is determined by either the v1 pulses in the a/bc1j1v1 signals or the h4 multiframe detection circuits, as described in an earlier section. the tu/vt pointer bit assignment for the v1 and v2 bytes is shown below. the alignment is necessary to determine the starting locations of the v5 byte and the other bytes that are carrying the ds1 or e1 format. i = increment bit d = decrement bit n = new data flag bit (enabled = 1001 or 0001/1101/1011/1000, normal or disabled = 0110 or 1110/0010/0100/0111) ss-bits (vt size) = 11 for ds1 (1544 kbit/s) and 10 for e1 (2048 kbit/s) pointer bytes bit assignment the pointer value is a binary number with a range of 0 to 103 for the ds1 (1544 kbit/s) and 0 to 139 for the e1 (2048 kbit/s) format. the pointer offset indicates the offset from the v2 byte to the v5 byte in the vt1.5/tu-11 or tu-12/vt2 mapping. the pointer bytes are not counted in the offset calculation. the pointer offset arrange- ment for this format is shown below. tu/vt pointer offset locations v1 byte v2 byte 1234567812345678 nnnnss-bits ididididid v1 105 106-138 139 v2 0 1-33 34 v3 35 36-68 69 v4 70 71-103 104 vt2/tu-12 v1 78 79-102 103 v2 0 1-24 25 v3 26 27-50 51 v4 52 53-76 77 vt1.5/tu-11
temx8 txc-04218 - 64 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 sixteen independent pointer-tracking state machines are used in the temx8, one for each channel in the a and b drop buses. the values of the v1/v2 pointer bytes in each multiframe are provided in registers x+183h and x+184h for the a side, and registers x+203h and x+204h for the b side. the pointer tracking algorithm is illustrated in the following figure 32 . the pointer tracking state machine is based on the pointer tracking state machine defined in the etsi and ansi requirements. when control bit ptalte (bit 1, 01bh) is 0, the transition from ais to lop is disabled (shown dotted). figure 32. vt/tu pointer tracking state machine the ais indication (a/bnais) is provided in bit 3 of registers x+111/x+191h. the lop indication (a/bnlop) is provided in bit 2 of registers x+111/x+191h. the ndf indication (a/bnndf) is provided in bit 1 of registers x+111/x+191h. the wrong size indication (a/bnsize) is provided by bit 0 of registers x+111/x+191h. the positive justification counter is located in registers x+120h for the a side and x+1a0h for the b side. the negative justification counter is located in registers x+121h for the a side and x+1a1h for the b side. inc lop ais dec norm 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x any_point dec_ind (decr. offset) 3 x new_point (accept new offset) 3 x new_point (accept new offset) 3 x any_point ndf_enable (accept new offset) 8 x inv_point (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 8 x inv_point (offset undefined) ndf_enable (accept new offset) 3 x ais_ind (offset undefined) 8 x ndf_enable (offset undefined) ndf_enable (accept new offset) ndf_enable (accept new offset) ndf_enable (accept new offset) 3 x new_point (accept new offset) 3 x any_point inc_ind (incr. offset) 3 x ais_ind (offset undefined) ndf
temx8 txc-04218 - 65 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 pointer tracking state machine states definition notes: 1. the active offset value is defined as the accepted current phase of the vt1.5/vt2 in the state norm_state and is undefined in other states. 2. ndf enabled is defined as one of the following bit patterns: 1001, 0001, 1101, 1011, 1000. 3. ndf disabled is defined as one of the following bit patterns: 0110, 1110, 0010, 0100, 0111. 4. the remaining six ndf codes (0000, 0011, 0101, 1010, 1100 and 1111) result in an inv_point indication. the ndf code 1111 does not result in an inv_point indication if it is part of an ais_ind. 5. note that the new_point is also an inv_point. 6. 3 x new_point takes precedence over other events. 7. the second and third offset value received in 3 x new_point must be identical with the first. 8. the consecutive new_point counter is reset to 0 on a change of state, except for transitions occurring among the inc, dec, ndf and norm states. 9. the consecutive inv_point counter can be incremented in all states. the consecutive inv_point counter is not reset on a change of state. 10. the consecutive ais_ind counter is not reset on a change of state. 11. the consecutive ndf_enable counter is reset to zero on a change of ais to ndf state. otherwise the counter is not reset. 12. inc_ind/dec_ind causes the active offset value to be incremented/decremented, respectively. the subsequent detection of a 3 x new_point with an offset value equal to the offset value caused by inc_ind/dec_ind will not cause the new pointer flag to assert. 13. ss-bits match for ds1 is 11 and 10 for e1. event definition norm_point disabled ndf (0110, 1110, 0010, 0100, 0111) and match of ss-bits and receive pointer offset value equal to active offset value. ndf_enable ndf enabled (1001, 0001, 1101, 1011, 1000) and match of ss-bits and received pointer offset value in range. ais_ind pointer = 11111111 11111111 (ff hex, ff hex) inc_ind ndf disabled (0110, 1110, 0010, 0100, 0111) and match of ss-bits and a match of 8 or more of the 10 i and d bits. please note that this requirement dif- fers from the majority of i bits inverted and no majority of d bits received. dec_ind ndf disabled (0110, 1110, 0010, 0100, 0111) and match of ss-bits and a match of 8 or more of the 10 i and d bits. please note that this requirement dif- fers from the majority of d bits inverted and no majority of i bits received. inv_point not norm_point and not ndf_enable and not ais_ind and not {(inc_ind or dec_ind) and norm_state}. 8 x ndf_enable 8 consecutive ndf_ enable. 3 x ais_ind 3 consecutive ais_ind. 3 x any_point 3 x not ndf_enable and not 3 x ais_ind and not 3 x new_point. new_point disabled ndf (0110, 1110, 0010, 0100, 0111) and match of ss-bits and receive pointer offset value in range but not equal to the active offset value. 3 x new_point 3 consecutive new_point received.
temx8 txc-04218 - 66 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 overhead byte processing in addition to overhead byte (v5, j2, n2, and k4 bytes) processing, all four overhead bytes for both the a and b drop buses are written into single byte locations for the channel selected, every 500 microseconds. v5 byte processing the placement of bits within the v5 byte is shown below. bip-2 bits 1 and 2 are used for error performance monitoring. a bit interleaved parity scheme is used. one or two errors may be detected in the bip-2 comparison, and they are counted individually in an 8-bit counter when control bit block (bit 4, 01ah) is written with a 0. when control bit block is written with a 1, one or two parity errors are counted as a single block error. remote error indication (rei) a remote error indications (rei) is sent by the distant end when one or two errors are detected in the bip-2. otherwise it is set to 0. a remote error indication (rei) is counted in an 8-bit counter. remote failure indication (rfi) the remote failure indication (rfi) is normally used for byte synchronous applications and is normally set to 0. if the received value is equal to 1 five times consecutively, an rfi alarm indication (anrfi (bit 0, x+110h) for a drop or bnrfi (bit 0, x+190h) for b drop) is asserted. recovery occurs when bit 4 of the v5 byte is equal to 0 five times consecutively. signal label bits 5, 6, and 7 in the v5 byte provide a signal label. the temx8 provides the following monitoring circuits for the signal label: signal label mismatch detection unequipped detection vc ais detection remote defect indication detection there are two remote defect indication schemes defined: single bit rdi and three bit rdi. a common circuit per channel is used to detect both the three bit rdi states, and the single bit rdi state. the single bit rdi scheme is defined for sdh applications, while three bit rdi is defined for sonet applications. single bit rdi uses bit 8 in the v5 byte, while three bit rdi uses bits 5, 6 and 7 in the k4 byte, in conjunction with bit 8 in the v5 byte. three bit rdi (or enhanced rdi) allows the user to differentiate between server, connectivity, and payload defects. bit 8 in v5 is set equal to bit 5 in the k4 byte. bit 7 in the k4 byte is set to the inverse of bit 6 in the k4 byte in order to distinguish the enhanced version of rdi from single bit rdi. it should be noted that when bits 6 and 7 in the k4 byte are either 01 or 10, the rdi indication is also influenced by bit 8 in the v5 byte, as shown in the table below. when bits 6 and 7 are either 00 or 11, then rdi is determined solely by bit 8 in the bit12345678 bip-2 rei rfi signal label rdi msb lsb
temx8 txc-04218 - 67 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 v5 byte. this allows detection of an rdi originating from equipment that generates single bit rdi in the v5 byte. the following table lists the rdi defect indications that may be carried in the v5 and k4 bytes. three bit rdi and single bit rdi detection bit 8 v5 bit 5 k4 bit 6 k4 bit 7 k4 definition 0 0 0 0 no defect indications 0 0 0 1 no defect indications 0 0 1 0 remote payload defect, indicates a: - path label mismatch 0 0 1 1 no defect indications 0 1 0 0 no defect indications 0 1 0 1 no defect indications 0 1 1 0 no defect indications 0 1 1 1 no defect indications 1 0 0 0 remote defect indication (single bit rdi) 1 0 0 1 remote defect indication (single bit rdi) 1 0 1 0 remote defect indication (single bit rdi) 1 0 1 1 remote defect indication (single bit rdi) 1 1 0 0 remote defect indication (single bit rdi) 1 1 0 1 remote server defect; indicates a: - vt loss of pointer - vt ais detected - upstream ais detected (e1 or h1/h2 bytes). 1 1 1 0 remote connectivity defect - unequipped signal label - j2 mismatch - j2 loss of lock 1 1 1 1 remote defect indication (single bit rdi)
temx8 txc-04218 - 68 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 receive rdi detection and recovery the rdi alarm indications are defined in the table below. the number of consecutive events for detection and recovery is controlled by control bit v5al10 (bit 0, 01bh). the value of five is selected when the v5al10 con- trol bit is 0, and the value of ten is selected when the v5al10 control bit is 1. the number of detection and recovery events is valid for both three bit rdi and single bit rdi. rdi alarm definitions j2 byte processing there are two possible received j2 message sizes, 16 bytes (itu-t), or 64 bytes (ansi). the temx8 is capa- ble of dimensioning the transmit ram memory segment to the two sizes (16-byte or 64-byte). in addition, two modes of operation are provided for the 16-byte (itu-t) format: a microprocessor read mode, and a compare read mode. the following table lists the various control states associated with j2 processing. please note: the 64 byte ram is used on a shared basis with the j2 and n2 bytes. when the 64 byte ram is configured for a 64 byte j2 message, the n2 tandem connection feature is disabled. when the ram segment is configured for a 16 byte j2 byte message, two 16 byte segment are provided for the tandem connection feature when enabled, and for the j2 byte processing feature. anrdic bnrdic anrdip bnrdip anrdis bnrdis action 0 0 1 remote server defect indication, and a single bit rdi indication (bit 8 in the v5 byte). 0 1 0 remote payload defect indication. 1 0 0 remote connectivity indication. arnj2s1 (bit 1, x+010h) brnj2s1 (bit 1, x+080h) arnj2s0 (bit 0, x+010h) brnj2s0 (bit 0, x+080h action 0 0 receive j2 segment for channel n is configured for the 16-byte j2 message size. the bytes are written into the segment on a rotat- ing basis, starting with an arbitrary address. the j2 alarms are disabled. 0 1 receive j2 segment for channel n is configured for the 16-byte j2 message size, and comparison. the received 16-byte message is compared against a 16 byte microprocessor written message, that must be aligned to the starting address of the segment. the j2 alarms are enabled. 1 0 receive j2 segment for channel n is configured for the 64-byte j2 message size. the bytes are written into the segment on a rotat- ing basis, starting with an arbitrary address. the j2 alarms are disabled.
temx8 txc-04218 - 69 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 the itu-t defined 16-byte message consists of an alignment signal of (10000000 00000000) in the most sig- nificant bit (bit 1) of the message. the remaining 7 bits in each byte carry a data message, as illustrated below. itu-t 16-byte j2 message format the j2 16-byte message comparison works according to the following steps: 1. the microprocessor-written j2 byte segment should be initialized with a 16-byte message before enabling the j2 message comparison function. 2. the j2 message comparison function is then enabled (a/brnj2s0 = 1; a/brnj2s1 = 0) and immediately the j2 loss of lock alarm will be active (a/bnj2lol = 1) and the j2 trace identifier mismatch alarm will be inactive (a/bnj2tim = 0). this is the first step in the sequence - to initialize these alarms. 3. the incoming trace message is received, and the j2 comparison circuit searches for the j2 alignment pat- tern (bit 1: 1000...0 pattern). 4. j2 alignment pattern is found and the received stable trace message locations are updated with this incoming trace message. 5. the incoming trace message is then checked for three consecutive 16-byte message repeats. 6. if an error occurs before step 5 is completed, the sequence repeats, starting at step 3 (searching for the alignment pattern). 7. if the incoming trace message repeats three times in a row (after the alignment pattern is detected) without an error then this is an in-lock condition, and the j2 loss of lock alarm is reset (a/bnj2lol = 0). note that at this time the j2 mismatch alarm is still inactive (a/bnj2tim =0). 1 1 receive j2 segment for channel n is configured for the 64-byte j2 message size with alignment only. receiving an ascii cr/lf will synchronize an internal counter so that the next character after the last lf character will be written into the starting address of the 64 byte segment. the j2 alarms are disabled. bit12345678 1 16-byte j2 message 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 arnj2s1 (bit 1, x+010h) brnj2s1 (bit 1, x+080h) arnj2s0 (bit 0, x+010h) brnj2s0 (bit 0, x+080h action
temx8 txc-04218 - 70 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 8. once the incoming trace message is in-lock, the stable message, is compared against the microproces- sor-written reference message, byte for byte, for 16 bytes (the length of the multiframe message). if they compare, a match is declared, with no mismatch alarm (a/bnj2tim = 0). if they do not compare, a trace mismatch alarm is declared (a/bnj2tim = 1). there is no loss of lock alarm (a/bnj2lol = 0) because the incoming trace message is stable. 10. if the incoming message changes for three consecutive 16-byte messages, a loss of lock alarm (a/bnj2lol = 1) occurs and the sequence starts again from the beginning (step 2). n2 byte (tandem connection) the tandem connection feature is enabled by writing a 1 to control bit arntcen (bit 5, x+010h) for the a drop side or brntcen (bit 5, x+080h) for the b drop side, when control bit arnj2s1 (bit 1, x+010h) and brnj2s1 (bit 1, x+080h) is a 0. when control bit arnj2s1 (brnj2s1) is written with a 1, the tandem con- nection feature for the a drop (b drop) vt/tu is disabled. when control bit arntcen or brntcen is written with a 0, the tandem connection feature is disabled. the bit placement in a received n2 byte configured for tandem connection operation is shown below: tc bip-2 processing one or two errors may be detected in the tc bip-2 comparison, and they are counted individually in an 8-bit counter when control bit block (bit 4, 01ah) is written with a 0. when control bit block is written with a 1, one or two parity errors are counted as a single block error. tc ais indication a tandem connection ais alarm (antcais, bntcais) is declared when bit 4 is equal to 1 for five consecutive frames. recovery occurs when bit 4 is equal to 0 for five consecutive frames. tc rei processing an 8-bit counter (an tc rei counter, bn tc rei counter) is provided for counting the number of rei bits received as equal to 1 in bit 5 (tc rei) in the n2 byte. an rei indication indicates that the distant end has detected one or two errors when the bip-2 calculated for frame f-1 (all the bytes) is compared against the bip-2 value carried in the n2 byte in frame f. tc oei processing an 8-bit counter (an tc oei counter, bn tc oei counter) is provided for counting the number of oei bits received as equal to 1 in bit 6 (tc oei) in the n2 (z6) byte. an oei indication (a 1) indicates that the distant end has detected one or two errors when the bip-2 calculated for frame f-1 is compared against the bip-2 value carried in the v5 byte in frame f. bit12345678 bip-2 1 ais indication tc rei tc oei trace id tc rdi/odi msb lsb
temx8 txc-04218 - 71 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 bits 7 and 8 a multiframe alignment pattern, trace identifier message, tc rdi and tc odi indications are assigned to bits 7 and 8 in the frames of a 76-frame structure, as shown below: loss of multiframe (status bits antclm, bntclm) occurs when two consecutive frame alignment signals (1111 1111 1111 1110) are detected in error (i.e., one or more error in each fas). multiframe alignment is recovered when one consecutive non-errored fas are found. the tc trace identifier message comparison is based on the same state machine as that used for the 16-byte j2 message. the tc lock is removed when 3 messages are received in error and the antcll or bntcll alarm is declared. the tc lock is established when 3 valid, identical messages are received. a comparison is performed between the microprocessor-written tc and the contents of the incoming message. the message consists of tc trace id bytes 0 to 15. a tc trace identifier mismatch (antctm, bntctm) alarm is declared when any byte does not match. recovery occurs when there is a match between the microprocessor message and the accepted message. bit 8 in frame 73 is defined as a tandem connection remote defect indication (tc rdi). a tc rdi alarm occurs when a 1 has been detected in bit 8 in frame 73 for five consecutive multiframes (where each multi- frame is 38 ms). the tc rdi alarm state is exited when bit 8 is equal to 0 for five consecutive multiframes. an alarm indication is reported as antcrdi or bntcrdi. bit 7 in frame 74 is defined as a tandem connection outgoing defect indication (tc odi). a tc odi alarm occurs when a 1 has been detected in bit 7 in frame 74 for five consecutive multiframes (where each multi- frame is 38 ms). the tc odi alarm state is exited when bit 7 is equal to 0 for five consecutive multiframes. an alarm indication is reported as antcodi or bntcodi. tandem connection unequipped status unequipped tandem connection detection is provided. five or more consecutive received tandem connection n2 bytes equal to xx00 0000 result in a tc unequipped indication (antcuq, bntcuq). the alarm state is exited when five or more consecutive received tandem connection n2 (z6) bytes are not equal to xx00 0000. note that bits 1 and 2 of the n2 (z6) byte are masked (shown as x) and do not affect the detection. the xx represents a don?t care value and may be equal to a bip-2 value. frame no. n2 byte definition 1 - 8 frame alignment, 1111 1111 1111 1110 9 - 12 tc trace id byte no. 0 (1 crc-7) 13 - 16 tc trace id byte no. 1 (0 x x x x x x x) 17 - 20 tc trace id byte no. 2 (0 x x x x x x x) 21 thru 64 tc trace id bytes no. 3 thru 13 65 - 68 tc trace id byte no. 14 (0 x x x x x x x) 69 - 72 tc trace id byte no. 15 (0 x x x x x x x) 73 bit 7 = 0, bit 8 = tc rdi 74 bit 7 = tc odi, bit 8 = 0 75 bit 7 = 0, bit 8 = 0 76 bit 7 = 0, bit 8 = 0
temx8 txc-04218 - 72 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 overhead communications bit access microprocessor access is provided for the eight overhead communications bits (o-bits) carried in the two justi- fication control (jc) bytes in the multiframe format, e.g., in a 1544 kbit/s tributary, shown partially below. the bits in the justification control byte are numbered 1 through 8, starting with c1 as bit 1. o-bit placement in a 1544 kbit/s tributary in the receive direction, the eight o-bits are stored in 8-bit registers for each channel assigned for the a and b drop buses. the a side register location is x+18ah, and b side register location is x+20ah. the o-bit regis- ters are updated each multiframe with the two o-bit nibbles from the same multiframe. bits 7 through 4 in an o-bit register correspond to bits 3 through 6 (c1c2 oooo dr) in the first justification control byte, and bits 3 through 0 in an o-bit register correspond to bits 3 through 6 in the second justification control byte, as shown below. o-bit assignment memory map vt/tu receive interface the vt/tu interface provides user access to the 104 byte vc-11 or the 140 byte vc-12 with or without the overhead bytes. the vt/tu interface is enabled when control bits rnlint1 (bit 7, x+006h) and rnlint0 (bit 6, x+006h) are set to 11. the options associated with this interface are given in the following table. other bytes j2 byte jc byte 1 c1 c2 o(1) o(2) o(3) o(4) d r 24 bytes - information n2 byte jc byte 2 c1 c2 o(5) o(6) o(7) o(8) d r other bytes register76543210 o-bits o(1) o(2) o(3) o(4) o(5) o(6) o(7) o(8) rnsel (bit 2, x+006h) rnvtvc (bit 4, x+008h) interface selected 0 0 a side payload bytes provided. the v5, j2, n2, and k4 overhead bytes are not provided. the clock is gapped during the overhead byte times. a positive frame pulse determines the last bit of the frame. 0 1 a side payload bytes provided. the v5, j2, n2, and k4 overhead bytes are provided. a positive frame pulse determines the last bit of the frame. 1 0 b side payload bytes provided. the v5, j2, n2, and k4 overhead bytes are not provided. the clock is gapped during the overhead byte times. a positive frame pulse determines the last bit of the frame. 1 1 b side payload bytes provided. the v5, j2, n2, and k4 overhead bytes are provided. a positive frame pulse determines the last bit of the frame.
temx8 txc-04218 - 73 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 receive cross mapping applications the temx8 supports cross mapping applications in which a ds1 format is carried in a vc-12 for transport by a vt2/tu-12. the options associated with this feature are given in the following table. the cross mapping fea- ture control in the drop direction is independent of the add direction. please note: the cross connect feature will not be supported when the vt/tu interface for channel n is selected. line ais insertion an alarm indication signal (ais) is defined as an unframed all ones signal for both the ds1 (1544 kbit/s) and e1 (2048 kbit/s) line rates. line ais will be inserted into the interface data lead (including the vt/tu) interface for channel n for the drop bus alarms when enabled. in addition, the microprocessor can also force the ais state independent of the drop side alarms. when control bit rnsel is a 0, the a side drop bus vt/tu is selected. when rnsel is a 1, the b side drop bus vt/tu is selected. the following is a list of alarms and enable bits for controlling the insertion of receive line ais. - when control bit rnaise is a 1 and the side that is active (rnsel bit state): - drop bus loss of clock (adloc, bdloc) when dlcae is a 1 - drop bus ais alarm (axuais, bxuais) when heaise and uaise are 1 - loss of pointer alarm (anlop, bnlop) - vt/tu ais detected (anais, bnais) - unequipped signal label (anuneq, bnuneq) when uqaise is a 1 - mismatch signal label (ansler) when plsaise is a 1 - j2 loss of lock alarm (anj2lol, bnj2lol) when j2aisen is a 1 - j2 mismatch alarm (anj2tim, bnj2tim) when j2aisen is a 1 - vt ais detected (anvcais, bnvcais) when vcaise is a 1 - tc loss of multiframe (antclm, bntclm), tc enabled and tctae is a 1 - tc loss of lock alarm (antcll, bntcll), tc enabled and tctae is a 1 - tc mismatch alarm (antctm, bntctm), tc enabled and tctae is a 1 - tc unequipped alarm (antcuq, bntcuq), tc enabled and tcuae is a 1 - tc ais detected (antcais, bntcais), tc enabled and tcaise is a 1 - control bit rnsais is a 1) - fifo alarm (anrffe, bnrffe) - when control bit rnaise is a 0: - control bit rnsais is a 1) note: the ais will be sent for two to three multiframes when a receive fifo error occurs. bit 7, x+012h/082h vt/tu select register a/b drop rne1sl, bit 4, x+006h operation 0 0 ds1 asynchronous format demapped from a vt1.5/tu-11. 01not used. 1 0 cross mapping. ds1 asynchronous format demapped from a vt2/tu-12. 1 1 e1 asynchronous format demapped from a vt2/tu-12.
temx8 txc-04218 - 74 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 receive interface the temx8 provides the user with three interface choices per channel. the options associated with this inter- face are given in the following table. the receive interface selection is independent of the transmit interface selection. the line interface rate is selected according to the following table: transmit interface the temx8 provides the user with three interface choices per channel. the options associated with this inter- face are given in the following table. the transmit interface selection is independent of the receive interface selection. rnlint1 (bit 7, x+006h) rnlint0 (bit 6, x+006h) rnoutl (bit 5, x+006h) interface selected 0 0 0 all interface leads forced to the high impedance state. 0 0 1 all interface leads forced to the 0 state. 0 1 x nrz interface selected. 1 0 x rail interface selected. 1 1 x vt/tu interface selected. rne1sl (bit 4, x+006h) interface rate selected 0 ds1 rate (1.544 mbit/s) 1 e1 rate (2.048 mbit/s) tnlint1 (bit 7, x+002h) tnlint0 (bit 6, x+002h interface selected 0 0 not used. 0 1 nrz interface selected. 1 0 rail interface selected. 1 1 vt/tu interface selected.
temx8 txc-04218 - 75 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 interface rate selection the line interface rate is selected according to the following table: vt/tu interface the vt/tu interface is selected when control bits tnlint1/0 (bits 7 and 6, x+002h) are set to 11. the tnsel1/0 (bits 1 and 0, x+006h) and rnsel (bit 2, x+006h) control bits determine the drop buses and add buses from which a vt/tu is dropped and added. the vt/tu interface is not valid for dual unidirectional ring mode of operation (tnsel1/0 are 11). four framing pulse lead references are provided: vta1.5 (vt1.5s for a add bus), vta2 (vt2s for a add bus, vtb1.5 (vt1.5s for b add bus) and vt2 (vts for b add bus). the over- head byte option associated with this interface is selected according to the following table: codec when the rail interface is selected, the codec may be configured for the ami code, or b8zs/hdb3. when control bit tnb8zs (bit 2, x+002h) is set to 0, the codec is configured for the ami line code for both the ds1 and e1 line rates. when this control bit is set to 1, the b8zs line code is selected for the ds1 line rate, and the hdb3 line code is selected for the e1 rate. a coding error is processed in the following way: a string of 16 or more zeros is counted as a coding violation when the line code is ami (ds1 or e1). a string of more than 4 zeros is counted as a coding violation when the line code is hdb3 (e1). a string of more than 8 zeros is counted as a coding violation when the line rate is b8zs (ds1). coding violation are counted in a 16 bit counter in addition to one second counters. when the interface for channel n is selected for a nrz interface, the negative rail lead may be used to input either an external loss of signal indication or external coding violations. when control bit exnlos (bit 1, x+003h) is set to 0, external coding may be counted. when set to 1, an external loss of signal may be inputted. an external loss of signal indication must be present for a minimum of 8 clock cycles (ds1 or e1). the active sense associated with the external loss of signal indication is controlled by control bit exnlosp (bit 0, x+003h). when control bit exnlosp is a 1, the sense is active high. external violations are counted when tlosn is high and the selected tclkn edge occurs. tclkn edge selection is done with control bit tnclki . tne1sl (bit 4, x+002h) interface rate selected 0 ds1 rate (1.544 mbit/s) 1 e1 rate (2.048 mbit/s) tnvtvc (bit 1, x+007h) overhead byte access 0 gapped output clock. the overhead bytes v5, j2, n2, and k4, in the data stream are not clocked in. the clock is gapped during the overhead byte times. 1 symmetrical output clock. the overhead bytes in the data stream are not clocked in except for bits 1 and 2 in the k4 byte. bits 3 through 8 in the k4 byte are ignored. bits 1 and 2 are inserted and transmitted from the vt/tu interface. bits 1 and 2 define an extended signal label and virtual concatena- tion information pertaining to the payload.
temx8 txc-04218 - 76 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 loss of signal detection the rail interface only is monitored for a loss of signal. a loss of signal alarm (tnlos) for the ds1 line rate is declared when no transitions are detected on the positive and negative rail leads for 175 +/- 75 consecutive pulse positions. recovery occurs when the average pulse density of at least 12.5% occurs over 175 +/- 75 pulse positions. a loss of signal alarm for the e1 line rate is declared when no transitions are detected on the positive and neg- ative rail leads for 256 consecutive pulse periods. recovery occurs when there are at least 32 transitions counted on the positive and negative rail leads for 256 consecutive clock cycles. clock inversion the transmit data for each of the rail and nrz interfaces can be clocked in on either negative or positive tran- sitions of the input clock for each channel. when control bit tnclki (bit 3, x+002h) is a 0, transmit data is clocked in negative transitions of the input clock. when a 1 is written to this control bit, data is clocked in on positive transitions of the clock. for the vt/tu interface selection, when control bit tnclki is set to 0, the framing pulses are clocked out posi- tive transitions of the output clock, while data is clocked in on negative transitions of the clock. when control bit tnclki is set to 1, the framing pulses are clocked out negative transitions of the output clock, while data is clocked in on positive transitions of the clock. nrz data inversion an option is provided which enables the data stream to be inverted when the nrz interface only is selected independently in both the receive and transmit directions. when control bit tnnrzp (bit 5, x+002h) is set to 1, the nrz data stream will be inverted. line ais detection the transmit nrz and rail line signals are monitored for line ais. a line ais condition is defined as an all ones unframed signal for both the ds1 and e1 line rates. a line ais alarm (tnais) for the ds1 line rate is declared when 99.9% or more ones are detected in the received signal for a period of 48 ms. recovery occurs when the receive signal has fewer than 99.9% of ones in a 48 ms period. an ais alarm for the e1 rate is declared when the signal has two or less zeros in each of two consecutive dou- ble frame period (four frames). recovery occurs when each of two consecutive double frame periods contain three or more zeros. line ais generation the temx8 provides the ability to generate a line ais signal on a per channel basis. line ais for the ds1 (1544 kbit/s) and for the e1 (2048 kbit/s) line rate is defined as an unframed all ones signal. the following is a list of alarms and enable bits for controlling the insertion of transmit line ais. - when control bit tnaise is a 1 and any of the following alarms occur: - transmit loss of clock (tnloc) - transmit loss of signal (tnlos) when the rail interface is selected - external loss of signal (tnlos) when the nrz interface is selected and control bit exnlos is a 1 - when control bit tnsais is a 1 - when control bit tnaise is a 0: - when control bit tnsais is a 1 note: when control bit tnaise is a 0 and the transmit loss of clock (tnloc) alarm occurs, transmit line ais may be generated regardless of the state of control bit tnsais.
temx8 txc-04218 - 77 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 transmit cross mapping applications the temx8 supports cross mapping applications in which a ds1 format is carried in a vc-12 for transport by a vt2/tu-12. the options associated with this feature are given in the following table. the cross mapping fea- ture control in the add direction is independent of the drop direction. please note: the cross connect feature will not be supported when the vt/tu interface for channel n is selected. overhead byte insertion in general, the transmitted overhead byte states (v5, j2, n2, and k4 bytes) for each channel may be controlled by internal alarm states, or by the microprocessor. v5 byte the placement of bits with in the v5 byte is shown below. bip-2 bits 1 and 2 in the v5 byte carry a bit interleaved parity - 2 (bip-2). bit 1 is set so that the parity of all odd num- bered bits (1, 3, 5, and 7) in all the bytes in the previous vc-11/vc-12 is even, while bit 2 is set similarly for all even numbered bits. the calculation includes all of the payload and overhead bytes, but excludes the v1, v2, v3 and the v4 bytes. bip-2 errors can be transmitted by setting control bit atnfb2 (bit 3, register x+064h) or btnfb2 (bit 3, regis- ter x+0d4h) for the a and b side add buses respectively. remote error indication bit bit 3 carries a remote error indication (rei). this bit carries the block error indication from the incoming bip-2 comparison performed in the drop direction for the vt/tu selected for channel n. the temx8 provides a syn- chronization circuit between the dropped tu/vt and the added tu/vt to prevent lost counts due to differences in clock phases between the drop and add sides. single rei can be transmitted by setting control bit atnffb (bit 6, register x+065h) or btnffb (bit 6, register x+0d5h) for the a and b side add buses respectively. remote failure indication the transmit remote failure indication for the vt/tu selected is controlled by control bit atnrfi (bit 7, x+064h) or btnrfi (bit 7, x+0d4h) for the a and b side add buses respectively. when control atnrfi or btnrfi is set to 1, bit 4 in the v5 byte is transmitted as a 1. bit 7 x+01ah, 08ah vt/tu select register a/b add tne1sl (bit 4, x+002h) operation 0 0 ds1 asynchronous format mapped to a vt1.5/tu-11. 0 1 not used. 1 0 cross mapping. ds1 asynchronous format mapped to a vt2/tu-12. 1 1 e1 asynchronous format mapped to a vt2/tu-12. bit12345678 bip-2 rei rfi signal label rdi msb lsb
temx8 txc-04218 - 78 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 signal label bits 5, 6, and 7 provide a signal label for the distant end. there are eight possible states. any value other then 000 represents an equipped vt/tu. the values written into atnsl1-3 (bits 5-3, register x+065h) and btnsl1-3 (bits 5-3, register x+0d5h0, for the a and b side add buses respectively, are transmitted in the v5 byte bits 5-7. remote defect indication the temx8 supports both single bit and three bit rdi operation. the selection of single bit or three bit rdi is determined by the value written to control bit tndisb (bit 0, x+007h). when control bit tndisb is set to 0, three bit rdi operation is selected. when this control bit is set to 1, single bit rdi is selected. single bit rdi bit 8 in the v5 byte provides a single bit rdi state, as indicated in the following table. itu recommendation g.707 recommends that bits 5, 6, and 7 in the k4 byte be transmitted as 000 or 111. a single bit rdi state is sent for the following unlatched alarm conditions in the v5 overhead byte of the vt/tu selected for the a or b add bus, depending on the states of the rnsel (active bus selected), tnsel1 and tnsel0 (bus enabled) control bits. rdi is sent for a minimum of 20 multiframes (500 microseconds per multi- frame). - when control bit rdi enable (rndien) is 1: - drop bus loss of clock (adloc, bdloc) when dlcre is a 1 - upstream ais in h1/h2 or the e1 byte (axuais, bxuais), when heaise and urdie are a 1 - vt/tu ais (anais, bnais) - vt/tu loss of pointer (anlop, bnlop) - vc ais (anvcais, bnvcais) when vcrdie is a 1 - unequipped (anuneq, bnuneq), when uqrdie is 1 - j2 loss of lock (anj2lol, bnj2lol), when j2rdie is a 1 - j2 mismatch (anj2tim, bnj2tim), when j2rdie is 1 - microprocessor writes a 1 to atnrdis, btnrdis - when rdi enable (rndien) is 0: - microprocessor writes a 1 to atnrdis, btnrdis bit 8 v5 definition 0 no defect indications. 1 remote defect indication
temx8 txc-04218 - 79 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 three bit rdi in addition to using bit 8 in the v5 byte, bits 5, 6, and 7 in the k4 byte are also used. bit 8 in the v5 byte works in conjunction with bits, 5, 6, and 7 in the k4 byte to provide the following possible rdi states. three bit rdi is recommended for ansi north american applications: three bit rdi permits the user to differentiate between the sonet alarms at the distant end. the three rdi alarms are defined as: remote server defect indication, remote connectivity defect indication, and remote connectivity defect indication. the remote server defect indication has the highest priority, followed by the remote connectivity defect indication and the lowest priority, remote payload defect indication. a remote defect indication is sent for the following unlatched alarm conditions in the v5 and k4 overhead bytes of the vt/tu selected for the a or b add bus, depending on the states of the rnsel (active bus selected), tnsel1 and tnsel0 (bus enabled) control bits. a remote defect indication is sent for a minimum of 20 multiframes (500 microseconds per multiframe). - when control bit rdi enable (rndien) is 1, a remote server defect indication is sent for: - drop bus loss of clock (adloc, bdloc) when dlcre is a 1 - upstream ais in h1/h2 or the e1 byte (axuais, bxuais), when heaise and urdie are a 1 - vt/tu ais (anais, bnais) - vt/tu loss of pointer (anlop, bnlop) - vc ais (anvcais, bnvcais) when vcrdie is a 1 - microprocessor writes a 1 to atnrdis, btnrdis - when control bit rdi enable (rndien) is 1, a remote connectivity defect indication is sent for: - unequipped (anuneq, bnuneq), when uqrdie is 1 - j2 loss of lock (anj2lol, bnj2lol), when j2rdie is a 1 - j2 mismatch (anj2tim, bnj2tim), when j2rdie is 1 - microprocessor writes a 1 to atnrdic, btnrdic - when control bit rdi enable (rndien) is 1, a remote payload defect indication is sent for: - mismatch signal label (ansler, bnsler) when psrdie is a 1 bit 8 v5 bit 5 k4 bit 6 k4 bit 7 k4 definition 0 0 0 no defect indications. 0 0 1 no defect indications. 0 1 0 remote payload defect - path label mismatch 0 1 1 no defect indications. 1 0 0 single bit remote defect indication 1 0 1 remote server defect - vt loss of pointer - vt ais detected - upstream ais detected (e1 or h1/h2 bytes). 1 1 0 remote connectivity defect - unequipped signal label - j2 mismatch - j2 loss of lock. 1 1 1 single bit remote defect indication.
temx8 txc-04218 - 80 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 - microprocessor writes a 1 to atnrdip, btnrdip - when control bit rdi enable (rndien) is 0: - remote server defect indication is sent when control bit atnrdis, btnrdis is a 1 - remote connectivity defect indication is sent when control bit atnrdic, btnrdic is a 1 - remote payload defect indication is sent when control bit atnrdip, btnrdip is a 1 j2 byte the j2 byte may be used to send a trail trace message. the trail trace message may be 16 bytes or 64 bytes in length. the 64 byte ram segment allocated for the j2 message will be used on a shared basis with the n2 byte according to the following table. n2 byte the n2 byte may be used for a tandem connection application. the tandem connection feature works in con- junction with control bits atnj2tsz/btnj2tsz (bit 0, x+063h, x+0d3h) according to the following table. the bit placement of the transmitted n2 (z6) byte is as shown below: atnj2ten (bit 1, x+063h) btnj2ten (bit 1, x+0d3h) atnj2tsz (bit 0, x+063h) btnj2tsz (bit 0, x+0d3h) operation 0 0 transmit j2 ram segment is configured for a 16 byte message. the bytes will be transmitted starting with an arbitrary address. please note the temx8 does not calcu- late the crc-7 for the message, nor does it insert the 1000... pattern transmitted the message. 0 1 transmit j2 ram segment is configured for a 64 byte message. the bytes will be transmitted starting with an arbitrary address. 1 x the j2 byte is transmitted as 00h. the 16 byte message written into the j2 ram seg- ment is ignored. atnj2tsz (bit 0, x+063h) btnj2tsz (bit 0, x+0d3h) atntcen (bit 2, x+063h) btntcen (bit 2, x+0d3h) operation 0 0 tandem connection feature is disabled. the value written to registers x+061h (a side n2 byte) for the a side, and x+0d1h (b side n2 byte) for the b side are transmitted. 0 1 tandem connection feature is enabled. the 16 byte trail trace message is written to registers x+03ch to x+04bh for the a side, and x+0ach to x+0bbh for the b side. 1 0 tandem connection feature disabled. the value written to registers x+061h (a side n2 byte) for the a side, and x+0d1h (b side n2 byte) for the b side are transmitted. 1 1 tandem connection feature is enabled. however, the value written to registers x+061h (a side n2 byte) for the a side, and x+0d1h (b side n2 byte) for the b side is repeated 16 times as the trail trace message. bit12345678 bip-2 1 ais indication tc rei tc oei (febe) trace id tc rdi/odi msb lsb
temx8 txc-04218 - 81 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 tc ais generation bit 4 in the n2 byte is defined as an ais indication. when control bit antcais (bit 4, x+113h) or bntcais (bit 4, x+193h) is a 1, bit 4 is transmitted as a 1. bits 7 and 8 the temx8 will construct and transmit the 76 frame sequence in bits 7, and 8. a multiframe alignment pattern, trace identifier message, tc rdi and tc odi indications are assigned to bits 7 and 8 in the frames of a 76-frame structure, as shown below. the temx8 will generate the multiframe pattern specified for frames 1 through 8. this will followed by inserting the 16 byte message written to the 16 byte n2 ram segment by the microprocessor, which is followed by the insertion of tc rdi and tcodi. please note the temx8 does not cal- culate the crc-7 for the message, nor does it insert the 1000... pattern transmitted the message. tc rdi generation bit 8 in frame 73 is defined as a tandem connection remote defect indication (tc rdi). a tc rdi alarm is generated for the following unlatched alarm indications. tc rdi is sent for a minimum of 10 times. - when tc enable (tcnre) is a 1 and the rnj2s1 of the corresponding drop bus is 0. - drop bus loss of clock (adloc, bdloc) when dlcte is a 1 - drop bus ais alarm (axuais, bxuais) when heaise and ustce are 1 - loss of pointer alarm (anlop, bnlop) - vt/tu ais detected (anais, bnais) - unequipped signal label (anuneq, bnuneq) when uqtce is a 1 - mismatch signal label (ansler) when plstce is a 1 - j2 loss of lock alarm (anj2lol, bnj2lol) when j2tce is a 1 - j2 mismatch alarm (anj2tim, bnj2tim) when j2tce is a 1 - vt ais detected (anvcais, bnvcais) when vctce is a 1 - tc loss of multiframe (antclm, bntclm) - tc loss of lock alarm (antcll, bntcll) - tc mismatch alarm (antctm, bntctm) - tc unequipped alarm (antcuq, bntcuq) - a 1 written to atntcsr, btntcsr - when tc enable (tcnre) is a 0 - a 1 written to atntcsr, btntcsr frame no. n2 byte definition 1 - 8 multiframe alignment, 1111 1111 1111 1110 9 - 12 tc trace id byte no. 0 (1 c1 thru c7) 13 - 16 tc trace id byte no. 1 (0 x x x x x x x) 17 - 20 tc trace id byte no. 2 (0 x x x x x x x) 21 - 24 thru 61 - 64 tc trace id bytes no. 3 thru 13 65 - 68 tc trace id byte no. 14 (0 x x x x x x x) 69 - 72 tc trace id byte no. 15 (0 x x x x x x x) 73 bit 7 = 0, bit 8 = tc rdi 74 bit 7 = tc odi, bit 8 = 0 75 bit 7 = 0, bit 8 = 0 76 bit 7 = 0, bit 8 = 0
temx8 txc-04218 - 82 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 tc odi generation bit 7 in frame 74 is defined as a tandem connection outgoing defect indication (tc odi). an tc odi alarm indication is generated for the following unlatched alarm indications. tc odi is sent for a minimum of 10 times. - when tc enable (tcnre) is a 1 and the rnj2s1 of the corresponding drop bus is 0. - drop bus loss of clock (adloc, bdloc) when dlcte is a 1 - drop bus ais alarm (axuais, bxuais) when heaise and ustce are 1 - loss of pointer alarm (anlop, bnlop) - vt/tu ais detected (anais, bnais) - unequipped signal label (anuneq, bnuneq) when uqtce is a 1 - mismatch signal label (ansler) when plstce is a 1 - j2 loss of lock alarm (anj2lol, bnj2lol) when j2tce is a 1 - j2 mismatch alarm (anj2tim, bnj2tim) when j2tce is a 1 - vt ais detected (anvcais, bnvcais) when vctce is a 1 - tc loss of multiframe (antclm, bntclm) - tc loss of lock alarm (antcll, bntcll) - tc mismatch alarm (antctm, bntctm) - tc unequipped alarm (antcuq, bntcuq) - tc ais detected (antcais, bntcais), tc enabled and tcaise is a 1 - a 1 written to atntcso, btntcso - when tc enable (tcnre) is a 0 - a 1 written to atntcso, btntcso tc unequipped generation the temx8 provides the ability to generate a vt/tu tandem connection unequipped signal on a per channel basis when the tc feature is enabled for a channel. when control bit antcuq (bit 2, x+064h) or bntcuq (bit 2, x+0d4h) is a 1, a tc unequipped status is transmitted. the temx8 can generate a unequipped status byte with a valid bip-2 (bits 1 and 2, and the remaining bits in the byte equal to 0 (xx00 0000), or all bits in the n2 byte equal to 0 (0000 0000). when control bit tb2dis (bit 2, register 03bh) is a 0, a valid bip-2 is transmitted. overhead bytes - microprocessor written in addition to the j2 byte, the overhead bytes may also be transmitted with a microprocessor written value. the microprocessor written value has priority over any other source except unequipped or vt/tu ais. when con- trol bit atnv5bs (bit 0, x+064h) or btnv5bs (bit 0, x+0d4h) is written with a 1, the value written to register x+060h for the a side and register x+0d0h for the b side is transmitted in the v5 byte. when control bit atnk4pc (bit 1, x+065h) or btnk4pc (bit 1, x+0d5h) is written with a 1, the value written to register x+062h for the a side and register x+0d2h for the b side is transmitted in the k4 byte. when control bit atntcen (bit 2, x+063h) or btntcen (bit 2, x+0d3h) is written with a 0 (tc feature dis- abled), the value written to register x+061h for the a side and register x+0d1h for the b side is transmitted in the n2 byte. vt/tu ais generation the temx8 provides the ability to generate a vt/tu ais signal on a per channel basis. when a 1 is written to control bit atngais (bit 6, x+063h) or btngais (bit 6, x+0d3h) for channel n, a tu/vt ais is generated for corresponding bus. a tu/vt ais consists of all ones in the entire tributary signal, including bytes v1 through v4. a tu/vt ais will override a unequipped channel when set.
temx8 txc-04218 - 83 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 unequipped generation the temx8 mapper is capable of generating and sending an unequipped channel or unequipped supervisory channel over either the a or b buses or both buses for channel n. an unequipped vt/tu format consists of: normal ndf (0110) in the v1/v2 pointer bytes size bits equal to 11 in the v1/v2 pointer bytes for vc-11 and 10 for vc-12 pointer value equal to 78 (decimal) for vc-11 and 105 (decimal) for vc-12 v4 byte equal to 0 or the microprocessor written value payload bytes equal to 0 valid bip-2 value in the v5 byte all other bits in the overhead bytes equal to 0. an unequipped supervisory vt/tu format consists of: normal ndf (0110) in the v1/v2 pointer bytes size bits equal to 11 in the v1/v2 pointer bytes for vc-11 and 10 for vc-12 fixed pointer value equal to 78 (decimal) for vc-11 and 105 (decimal) for vc-12 v4 byte equal to 0 or the microprocessor written value valid j2 byte valid rei in the v5 byte valid bip-2 value in the v5 byte valid rdi value (single bit or three bit) k4 byte equal to 0 for single bit rdi mode; bits 1-4, 8 equal 0 for three bit rdi mode signal label equal to 0 in the v5 byte rfi bit in the v5 byte set to 0 n2 byte can be enabled for tc operation, otherwise it is set to 0 payload bytes equal to 0. the various states associated with an unequipped channel selection are shown in the table below. where n is equal to 1-8. note: control bits atntptv (bit 5, x+063h) and btntptv (bit 5, x+0d3h) must be set to 0 when generating unequipped or supervisory unequipped. anuqge (bit 4, x+063h) bnuqge (bit 4, x+0d3h) anuqsu (bit 3, x+063h) bnuqsu (bit 3, x+0d3h) action 0 x normal operation. 1 0 unequipped tu/vt generated 1 1 unequipped supervisory tu/vt generated
temx8 txc-04218 - 84 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 pointer generation the vt/tus that are added to the a and b add buses have fixed pointers references to the v1 pulse derived from either the drop side for drop bus timing or from the add side for add bus timing. the vt1.5/tu-11 is fixed with a pointer value equal 78, and for a vt2/tu-12 the pointer is fixed to a value of 105. v4 byte normally the v4 byte is transmitted with a value equal to 00h. when control bit atnv4bs (bit 0, x+066h) or btnv4bs (bit 0, x+0d6h) is written with a 1, the value written to register x+05eh for the a side and register x+0ceh for the b side is transmitted instead. v1 and v2 bytes normally the v1/v2 bytes and the vt/tu payloads and overhead bytes are transmitted with a fixed pointer. when control bit atntptv (bit 5, x+063h) or btntptv (bit 5, x+0d3h) is written with a 1, the value written to registers x+05ch and 05dh for the a side and register s x+0cch and x+0cdh for the b side are transmitted instead for the v1/v2 bytes. the payload and overhead bytes are still transmitted with fixed the equivalent fixed pointer values of 78 and 105. this permits a test pointer to be transmitted. add buses the two add buses, a and b, consists of leads supporting the combus interface. the possible interface selections, including bus timing, are according to the following table. abust abte add bus interfaces low x add bus timing mode. the output leads consists of data (a/ba(7-0)), parity, (a/bapar), and add indicator (a/badd ). the input leads consists of clock (a/baclk), c1, j1, and v1 marker pulses (a/bac1j1v1), and pay- load indication (a/baspe). high low drop bus timing mode. the output leads consists of data (a/ba(7-0)), parity, (a/bapar), add indicator (a/badd ), clock (a/baclk), c1, j1, and v1 marker pulses (a/bac1j1v1), and payload indication (a/baspe). the clock, c1j1v1, and spe signals are derived from their liked name drop bus. the v1 pulse is derived from either the v1 pulse present in the c1j1v1 signal, or from the h4 byte detectors. high high drop bus timing mode. the output leads consists of data (a/ba(7-0)), parity, (a/bapar), and add indicator (a/badd ). the clock (a/baclk), c1, j1, and v1 marker pulses (a/bac1j1v1), and payload indication (a/baspe) leads are tristated.
temx8 txc-04218 - 85 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 add bus parity selection the parity selection for two add buses, a and b add, is according to the following table: add indicator invert an option is provided that inverts the add indicator (aadd and badd ) leads. when a 1 is written to control bit addiv (bit 0, 03ah), the output sense of the two leads is active high when a time slot for channel n is being added to a bus. when set to 0, the output sense of the two leads is active low when a time slot for channel n is being added to a bus. force bus to a high impedance state an option is provided that can force either of the output add bus signals to a high impedance state, indepen- dent of the channel selections. when control bit bahze (bit 2, 03ah) for the b side or aahze (bit 1, 03ah) for the a side is written with a 1, the following add bus signals are forced to a high impedance state: data (a/bd(7-0), parity, (a/bpar), and add indicator (a/badd ). if enabled as output signals, the following leads are also forced to a high impedance state: clock (a/bclk), c1, j1, and v1 marker pulses (a/bc1j1v1), and the payload indication (a/bspe). force channel n to a high impedance state the data and add indication corresponding to a channel can be forced to a high impedance state in two way. the a and b add bus vt/tu selection register is written to 00h, or control bit anhighz (bit 0, x+065h) or bnhighz (bit 0, 0d5h) is written with a 1. add bus delay normally there is one clock cycle of delay between the add bus data (a/bd(7-0)) and the timing signals such as a/bspe (add bus timing), or timing signals from the corresponding drop bus in the drop bus timing mode. the delay may be increased to two clock cycles when control bit abod (bit 1, 03bh) is written with a 1. abpe (bit 5, 03ah) pado (bit 6, 03ah) add bus parity selection 0 0 odd parity is calculated for the output leads consisting of data (a/ba(7-0)) in the drop bus timing mode, and also the output leads: clock (a/baclk), c1, j1, and v1 marker pulses (a/bac1j1v1), and payload indica- tion (a/baspe) when they are provided as outputs in the drop bus timing mode. 0 1 odd parity is calculated for the data output leads (a/ba(7-0)). 1 0 even parity is calculated for the output leads consisting of data (a/ba(7-0)) in the drop bus timing mode, and also the output leads: clock (a/baclk), c1, j1, and v1 marker pulses (a/bac1j1v1), and payload indica- tion (a/baspe) when they are provided as outputs in the drop bus timing mode. 1 1 even parity is calculated for the data output leads (a/ba(7-0)).
temx8 txc-04218 - 86 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 test functions prbs pattern generator and analyzer each ds1 or e1 channel has a prbs generator and analyzer. the prbs pattern is selectable, either a 2 15 -1 or 2 20 -1 pattern. the 2 15 -1 pattern is unframed and is defined in recommendation o.151, and t1m1.3/92-006r3. the 2 20 -1s pattern, referred to as a qrs pattern, is unframed and is defined in t1.403-1995 and t1m1.3/92-006r3. when control bit tnprn (bit 2, x+004h) is a 0, the prbs pattern is defined as 2 15 -1. the test pattern generator is enabled when control bit tnptg (bit 5, x+004h) is a 1. the analyzer is enabled when control bit tnanz (bit 4, x+004h) is a 1. in addition, on a global basis, when control bit prbsg (bit 1, 018h) is a 0, the generators are configured for the transmit direction and when set to 1, are configured for the receive direction. when control bit prbsa (bit 3, 018h) is 0, all analyzers are in the receive direction and when set to 1 are configured for the transmit direction. note that when the generators are replaced in the receive path, a channel must have a vt/tu selected for the generator to operate. an out of lock alarm (cnool (bit 2, x+100h)) is provided when the prbs analyzer is enabled. an out of lock alarm occurs when there is a bit mismatch in the analyzed prbs pattern. recovery occurs when: the analyzed data is in lock for the 2 15 -1 pattern for more then 25 clock cycles. the analyzed data is in lock for the 2 20 -1 pattern for more then 32 clock cycles. figure 33 shows the placement of the prbs generator and analyzer. bip-2 error generation for each channel, a bip-2 error may be transmitted in the v5 byte. when control bit atnfb2 (bit 3, x+064h) or btnfb2 (bit 3, x+0d4h) is set to a 1, the transmitted bip-2 is transmitted inverted from its calculated value for one frame. in order to send another error, the control bit must be first written with a 0. rei error generation for each channel, an rei error may be transmitted in the v5 byte. when control bit atnffb (bit 6, x+065h) or btnffb (bit 6, x+0d5h) is set to a 1, the rei value will be transmitted as a 1 once in the next available v5 byte. a pending rei error as a result of a bip-2 error, shall be queue, until completion of sending the error is complete. in order to send another error, the control bit must be first written with a 0. loopbacks the temx8 supports two loopbacks on the ds1/e1 line side: facility and line loopback on a per channel basis. bidirectional loopback occurs when facility and line loopback are simultaneously enabled. it also supports a combus sonet/sdh loopback. the three loopbacks are illustrated in figure 33 . note that the facility and line loopbacks are not supported when the vt/tu line interface is selected. the selection of the loopbacks is according to the following table: facility loopback enables the transmit ds1 or e1 data and clock signals to be looped back as the receive data and clock signals. the transmit data is sent for the vt/tu selected. lnlbk (bit 1, x+004h) fnlbk (bit 0, x+004h) loopback selection 0 0 off 0 1 facility loopback enabled. 1 0 line loopback enabled. 1 1 bidirectional loopback enabled.
temx8 txc-04218 - 87 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 33. loopback, line ais and prbs generator/analyzer line loopback enables the received ds1 or e1 data and clock signals to be looped back as transmit signals. the ds1 or e1 line signals at the input are disabled. the vt/tu are demapped and mapped according to the vt/tu selection registers. when control bit rnlais (bit 0, x+000h) is a 1, line ais is outputted for the receive rail or nrz interface while the receive data for the vt/tu is simultaneously looped back. when rnlais is set to 0, the receive data for the vt/tu is outputted in addition to being looped back. rnlais is enabled only when line loopback is enabled. the rnclki (bit 3, register x+000h) and tnclki (bit 3, register x+002h) control bits must be programmed for opposite edges for this loopback. bidirectional loopback enables the transmit side clock and data to be looped back as the output at the receive interface. the output of the demapper is looped back as transmit data (as with line loopback, the rnclki and tnclki control bits must be programmed for opposite edges). combus sdh/sonet local loopback is enabled when control bit clpbk (bit 4, 019h) is written with a 1. this mode is valid in either the add bus or drop bus timing modes. timing is derived from the selected mode. the vt/tu are mapped and demapped according to the vt/tu selection registers. no vt/tu are passed to the demapper from either of the drop buses during combus loopback. combus loopback is valid only when control bit dv1sel (bit 2, register 019h) is a 1. combus loopback is valid from a add to a drop and b add to b drop. resets the temx8 has several reset options. these include the following: hardware reset (reset lead) software reset (reseth), bit 0 - 006h a and b drop reset (dreset), bit 0 - 039h a and b add reset (treset), bit 0 - 03ch per channel a drop reset (dachnr), bit 0 - x+011h per channel b drop reset (dbchnr), bit 0 - x+081h per channel add reset (tnreset), bit 0 - x+009 reset all channel counters (resetc), bit 5 - 01ah mapper demapper combus local loopback facility loopback loopback line add bus t1/e1 line drop bus ais from rx alarms rnaise ?1? clpbk rnsais ?1? tnsais tnaise lnlbk rnlais (only when lnlbk=1) ?1? fnlbk t1/e1 line tx rx channel n 1 0 0 1 0 1 0 1 1 1 0 0 0 1 0 1 ?1? 1 0 prbs generator tntpg prbsg prbs analyzer 0 1 tntpg prbsg 0 1 prbsa
temx8 txc-04218 - 88 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 all of the software reset bits except for reseth, are not self-clearing. a 0 must be written to these bits before another reset can take place. hardware reset when an active low pulse is applied to the reset lead for a minimum duration of 150 nanoseconds after power is applied, this pulse clears all performance counters and latched alarms, resets the control bits, and ini- tializes the internal fifos, and state machines. the microprocessor must wait at least 4 microseconds before the memory map states are written to. this enables an internal state machine to cycle through and clear all internal ram locations. software reset the software reset bit reseth (bit 0, 006h) is equivalent to the hardware reset bit. when a 1 is written to this control bit, it clears all performance counters and latched alarms, resets the control bits, and initializes the internal fifos and state machines. the microprocessor must wait at least 4 microseconds before the memory map states are written to. this enables an internal state machine to cycle through and clear all internal ram locations. a and b drop reset writing a 1 to control bit dreset (bit 0, 039h) clears all performance counters and alarms, and initializes the internal fifos and state machines for all channels for the a and b drop buses. it does not clear the control bit settings. a dreset operation may cause the following latched alarms to be set if the latched alarms are enabled (see intr0, intr1 control bit description in memory map) while the operation is performed: lanlop, lbnlop, laxhoom, lbxhoom (x =1,2 or 3), ladpar, and lbdpar. a and b add reset writing a 1 to the control bit treset (bit 0, 03ch) clears all performance counters and alarms, and initializes the internal fifos and state machines for all channels for the a and b add buses. it does not clear the control bit settings. per channel a drop reset writing a 1 to control bit dachnr (bit 0, x+011h) clears all performance counters, and initializes the internal fifos and state machines for the a drop bus vt/tu channel selected. it does not clear the control bit settings, or latched alarms for the channel selected. per channel b drop reset writing a 1 to control bit dbchnr (bit 0, x+081h) clears all performance counters, and initializes the internal fifos and state machines for the b drop bus vt/tu channel selected. it does not clear the control bit settings, or latched alarms for the channel selected. per channel a and b add reset writing a 1 to control bit tnreset (bit 0, x+009h) clears all performance counters, and initializes the internal fifos and state machines for the a and b add bus vt/tu channel selected. it does not clear the control bit settings, or latched alarms for the channel selected. data throughput delay on the receive side (sonet/sdh to t1/e1) the nominal delay for t1 is approximately 62 s and for e1 is approximately 49 s. nominal conditions are no pointer movements, nominal t1/e1 clock frequency, and either no line coding (nrz) or ami line coding. b8zs line coding adds 5 s of delay, and hdb3 adds 2.5 s delay. on the transmit side (t1/e1 to sonet/sdh) the nominal delay for t1 is approximately 64 s and for e1 is approximately 42 s. the nominal conditions for the transmit side are the same as for the receive side. b8zs and hdb3 line coding also add the same delay.
temx8 txc-04218 - 89 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 pointer leak rate calculations the pointer leak rate register for each channel is 10 bits long (x+017h and x+018h for the a side, and x+067h and x+088h for the b side). the host processor must write the first eight bits (x+017h and x+067h) followed by the remaining two bits of the 10 bit register. if the pointer leak rate register is set to 000h the receive fifo in the desynchronizer is bypassed. notes: 1. the procedure described in notes 3 through 8 below must be performed independently for each of the 8 channels in the temx8. when both buses are used, the leak rate must be calculated independently for each bus. the following notes describe the actions for one channel on one bus. 2. the procedure shown in the diagram above uses a thirty-second sliding window with a resolution of one second. when implementing the pointer leak rate calculation, while gathering the data from the previous one second counter, the pm1s clock and microprocessor read should be synchronized. 3. the fifo leak rate register must first be set to a value of 13, (00dh) for ds1 or 10, (00ah) for e1. 4. measure thirty consecutive one-second samples from the positive and negative stuff counters being used. store all thirty difference values, i.e., s 1 = pos stuff count 1 - neg stuff count 1 , s 2 = pos stuff count 2 - neg stuff count 2 , and so on through s 30 = pos stuff count 30 - neg stuff count 30 . care should be taken to use the pair appropriate to the programmed configuration of the device. 5. calculate the leak rate: leak rate = the smaller of 1023, (3ffh) or (hex[int{3300/c}], hex[int{500/d}] if d > 2, hex[int{375/e}] if e > 2, hex[int{250/f}] if f > 2, hex[int{125/g}] if g > 2) where hex is the hexadecimal value, int is the integer value: c = absolute value [sum(s i to s 30+i )], d = absolute value [sum(s 27+i to s 30+i )], e = absolute value [sum(s 28+i to s 30+i )], f = absolute value [sum(s 29+i to s 30+i )], g = absolute value [s 30+i ] and i represents the number of times through the loop shown in the diagram (notes 5, 6 and 7). if the c is 0, 1, 2 or 3 set the leak rate to 1023, (3ffh). a pointer will be leaked before another arrives for uniform pointer arrivals. if d, e, f, or g > 2, faster pointer leaking accounts for a rapid change in pointer arrival rate (e.g., start up). 6. set the fifo leak rate register with the value between 1 and 1023, (3ffh) calculated above, then take another one-second sample (e.g., s 31 ). 7. recalculate the value of ?c?, ?d?, ?e?, ?f? and ?g? by discarding the oldest value and adding the newest value (i = i + 1). 8. continue to repeat the steps described in notes 5, 6 and 7 until ais, lop, los or ndf is received or until you reset the chan nel or restart the device. measure 1 second subt oldest add newest calculate leak rate measure 1 second set fifo leak rate set fifo leak rate < 30 sec 30 sec ais, lop, los, ndf, or reset (note 6) (note 7) (note 6) (note 5) fifo (note 4) (note 3) start add to sum power on,
temx8 txc-04218 - 90 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 jitter measurements equipment used in temx8 jitter measurements: hewlett-packard digital transmission analyzer:hp-3784a anritsu digital transmission analyzer:me520b anritsu stm/sonet analyzer:mp1560a jitter tolerance test the jitter tolerance test is performed by inserting various jitter levels at selected frequencies into the 2048 kbit/s and the 1544 kbit/s line input of the temx8, as shown in figure 34 and 35 . data is looped back at the sdh/sonet interface and dropped by the same temx8 device (see figure 36 ). the measured value is the maximum input jitter that the temx8 can tolerate at its input without generating bit errors in the loopback path. figures 36 are plots of the requirement listed in the table. figure 34. e1 (2048 kbit/s) jitter tolerance figure 35. ds1 (1544 kbit/s) jitter tolerance input jitter frequency requirement maximum input jitter tolerated (ui-pp) 10 hz >1.5 ui 62.563 2.4 khz > 1.5 ui 17.01 18 khz > 0.2 ui 2.518 100 khz > 0.2 ui 0.665 input jitter frequency requirement (ui pp) maximum input jitter (ui pp) f1 10 hz > 5.0 64 100 hz > 5.0 60 f2 500 hz > 5.0 40 1 khz > 1.9 20 f3 8 khz > 0.1 2.579 25 khz > 0.1 0.907 f4 40 khz > 0.1 0.68
temx8 txc-04218 - 91 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 36. jitter tolerance measurements receiver transmitter pdh digital transmission analyzer e1/ds1 interface temx8 test fixture external loopback 155 mbit/s jitter tolerance - e1 rate 0.1 1 10 100 10 100 1000 10000 100000 input jitter frequency (hz) input jitter amplitude (ui-pp) maximum tolerated input jitter minimum requirement jitter tolerance - ds1 rate 0.1 1 10 100 10 100 1000 10000 100000 input jitter frequency (hz) input jitter amplitude (ui-pp) maximum tolerated input jitter minimum requirement
temx8 txc-04218 - 92 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 jitter transfer test a fixed jitter level of 1.0 ui (0.6 ui for 1000 hz) is inserted into the transmitted e1 and ds1 signal as illustrated below. the jitter value measured is achieved using the hp1/lp filter in the pdh receiver. the jitter transfer measurements are provided in the following figure 37 . figure 37. jitter transfer input jitter filter used jitter transfer (ui - pp, max) e1 rate jitter transfer (ui - pp, max) ds1 rate frequency unit interval 10 hz 1.0 ui f1-f4 (hp1/lp) .129 .129 40 hz 1.0 ui .0327 .0327 100 hz 1.0 ui .0131 .0131 250 hz 1.0 ui .0050 .0050 500 hz 1.0 ui .0031 .0029 1000 hz 0.6 ui .0016 .0012 temx8 hp-3784a test fixture digital transmission analyzer
temx8 txc-04218 - 93 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 38. e1 jitter transfer measurements figure 39. ds1 jitter transfer measurements jitter transfer - e1 rate 0.001 0.01 0.1 1 10 10 100 1000 input jitter frequency (hz) ui input measured output jitter transfer - ds1 rate 0.001 0.01 0.1 1 10 10 100 1000 input jitter frequency (hz) ui input measured output
temx8 txc-04218 - 94 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 mapping jitter measurement the following table lists the mapping jitter measurements, which are made with the following setup. these mapping jitter measurements were made in the absence of sts or vt(tu) pointer adjustments: note 1:these values are for further study. notes: 1. per recommendation itu-t g.783 (04/97). 2. per bellcore gr-253-core issue 2 dec. 95: rev 2 jan. 99. 3. these values are for further study. interface filter characteristics maximum output jitter (ui-pp) requirement measured value e1 - 2048 kbit/s f1-f4 (hp1/lp) (note 1) 0.027 f3-f4 (hp2/lp) < 0.075 ui 0.020 interface filter characteristics maximum output jitter (ui pp) requirement measured per g.783 (note 1) per bellcore (note 2) ds1 - 1544 kbit/s f1-f4 (hp1/lp) (note 3) 0.7 0.016 f1-f4 (hp1/lp) 0.1 0.7 0.015 anritsu temx8 hp-3784a e1 or ds1 interface stm/sonet analyzer test fixture digital transmission analyzer sonet data mp 1560a
temx8 txc-04218 - 95 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 combined jitter measurement the following table lists the combined jitter measurements. this measurement was performed using the follow- ing setup. tu-12 note 1: these values are written into the desynchronizer pointer leak rate registers. note 2: the limit corresponds to the pointer sequences shown in figure 40 for standard pointer test sequences, (t1 10 s, t2 > 0.75 s, t3 = 30 ms). the t3 value was constrained by test equipment limitations. value can vary depending on pointer sequence. pointer test sequence filter leak rate (hex) (note 1) maximum output jitter (ui - pp) requirement measured 1 single pointers of opposite polarity f1-f4 (hp1/lp) 52h 0.4 (note 2) 0.240 2 regular pointers plus one double pointer 52h 0.176 3 regular pointers with one missing pointer 52h 0.187 1 single pointers of opposite polarity f3-f4 (hp2/lp) 52h 0.075 (note 2) 0.010 2 regular pointers plus one double pointer 52h 0.010 3 regular pointers with one missing pointer 52h 0.010 anritsu temx8 hp-3784a e1 or ds1 interface stm/sonet analyzer test fixture digital transmission analyzer sonet data mp 1560a
temx8 txc-04218 - 96 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 40. tu-12 standard pointer test sequences t1 t2 t2 t3 r egular pointers with o ne miss ing value r egular pointers plus o ne double poiner s in g l e p oin te rs of o pposite polarity (r ef: itu -t g.783, f ig. 6-2)
temx8 txc-04218 - 97 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 vt1.5 notes: 1. per recommendation itu-t g.783. 2. per bellcore gr-253-core issue 2 dec. 95: rev 2 jan. 99. 3. these are values written into the desynchronizer pointer leak rate register normally the pointer leak rate register is controlled by the external microprocessor through the implementation of the pointer leak rate algorithm shown on page 89 . 4. ao is the mapping jitter generated by the device under test. please see mapping jitter measurement on the previous page. pointer test sequence filter leak rate value (hex) (note 3) maximum output jitter (ui pp) requirement measured g.783 (note 1) bellcore (note 2) single pointer adjustment = 30 s (f1) (f4) 10 hz -> 40 khz 3ffh 1.5 ao + 0.60 (note 4) 0.119 periodic vt1.5 pointer adjustment (26-1 pattern) = 0.35 s 25h 1.5 1.3 0.222 periodic vt1.5 pointer adjustment (continuous pattern) = 0.2 s 19h 1.5 1.3 0.600 periodic vt1.5 pointer adjustment (continuous pattern plus add) = 1 s t = 30 ms 7dh 1.5 1.9 0.218
temx8 txc-04218 - 98 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 41. vt1.5 standard pointer test sequences measurement period pointer adjustment initialization time 30 s single pointer adjustment test sequence 26 no pointer adjustment start of next 26 - 1 pattern periodic vt1.5 pointer adjustment test sequence (26-1 pattern) periodic vt1.5 pointer adjustment test sequence (continuous pattern) periodic vt1.5 pointer adjustment test sequence (continuous pattern plus add) pointer adjustment added pointer pointer adjustment cool down t
temx8 txc-04218 - 99 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 boundary scan introduction the boundary scan interface block provides a five-lead test access port (tap) that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test. the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. as shown in figure 42 , one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). the boundary scan capability is based on a test access port (tap) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. the boundary scan test bus interface consists of four input signals (test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs )) and a test data output (tdo) output signal. boundary scan signal timing is shown in figure 25 . the tap controller receives external control information via a test clock (tck) signal and a test mode select (tms) signal, and sends control signals to the internal scan paths. detailed information on the operation of this state machine can be found in the ieee 1149.1 standard. the serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. these three serial registers are connected in parallel between the test data input (tdi) and test data output (tdo) signals, as shown in figure 42 . the boundary scan function can be reset and disabled by holding lead trs low. when boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the temx8 device?s internal logic. during boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. boundary scan operation the maximum frequency the temx8 device will support for boundary scan is 10 mhz. the timing diagrams for the boundary scan interface leads are shown in figure 25 . the instruction register contains three bits. the temx8 device performs the following three boundary scan test instructions: the extest test instruction (000) provides the ability to test the connectivity of the temx8 device to external circuitry. the sample test instruction (010) provides the ability to examine the boundary scan register contents without interfering with device operation. the bypass test instruction (111) provides the ability to bypass the temx8 boundary scan and instruction registers. boundary scan reset specific control of the trs lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-up of the temx8. if boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the v il requirements listed in the ?input, output and input/output parameters? section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor.
temx8 txc-04218 - 100 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 figure 42. boundary scan schematic tap controller bypass register instruction register tdi tdo in out controls boundary scan serial test data core logic of temx8 boundary scan register signal input and output leads 3 device
temx8 txc-04218 - 101 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 multiplex format and mapping information sts-3/au-3 vt1.5/tu-11 (1.544 mbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the 84 vt1.5/tu-11s into an sts-3/au-3 spe. each sts-3 carries three sts-1s. column 1 in each sts-1/au-3 is assigned to carry the path overhead bytes. please note: the mapper does not insert the overhead bytes into the sts-1. sts-3/au-3 spe 1 2 3 27 12 3 4 27 vt vt vt vt 1 261 3 columns 1 31 59 87 1 87 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 1.5 # 28 1.5 # 1.5 # 28 vt vt vt vt vt vt vt 1.5 # 1.5 # 1.5 # 1.5 # 1.5 # 1.5 # 1.5 # 28 1.5 # 30 29 1 vt1.5 3 r r r r r r r r r r r r r r r r r r 87 vt 1.5 # 28 1 12 1 60 vt 1.5 # 1 28 1 1 2 27 bytes vt 2 # 2 vt 1.5 # note: columns 88, 89, 90, 175, 176 and 177 are fixed stuff. 2 58
temx8 txc-04218 - 102 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 sts-3/au-3 mapping (1.544 mbit/s) tu# vt/tu assignment 7 6 5 4 3 2 1 0 vt/tu column numbers tu# vt/tu assignment registers 7 6 5 4 3 2 1 0 vt/tu column numbers tu# vt/tu assignment 7 6 5 4 3 2 1 0 vt/tu column numbers 0 0 0 0 0 0 0 0 no tu selected 1 0 0 1 0 0 1 0 1 4 91 178 29 0 1 0 0 0 1 0 1 5 92 179 57 0 1 1 0 0 1 0 1 6 93 180 2 0 0 1 0 1 0 0 1 7 94 181 30 0 1 0 0 1 0 0 1 8 95 182 58 0 1 1 0 1 0 0 1 9 96 183 3 0 0 1 0 1 1 0 1 10 97 184 31 0 1 0 0 1 1 0 1 11 98 185 59 0 1 1 0 1 1 0 1 12 99 186 4 0 0 1 1 0 0 0 1 13 100 187 32 0 1 0 1 0 0 0 1 14 101 188 60 0 1 1 1 0 0 0 1 15 102 189 5 0 0 1 1 0 1 0 1 16 103 190 33 0 1 0 1 0 1 0 1 17 104 191 61 0 1 1 1 0 1 0 1 18 105 192 6 0 0 1 1 1 0 0 1 19 106 193 34 0 1 0 1 1 0 0 1 20 107 194 62 0 1 1 1 1 0 0 1 21 108 195 7 0 0 1 1 1 1 0 1 22 109 196 35 0 1 0 1 1 1 0 1 23 110 197 63 0 1 1 1 1 1 0 1 24 111 198 8 0 0 1 0 0 1 1 0 25 112 199 36 0 1 0 0 0 1 1 0 26 113 200 64 0 1 1 0 0 1 1 0 27 114 201 9 0 0 1 0 1 0 1 0 28 115 202 37 0 1 0 0 1 0 1 0 29 116 203 65 0 1 1 0 1 0 1 0 30 117 204 10 0 0 1 0 1 1 1 0 31 118 205 38 0 1 0 0 1 1 1 0 32 119 206 66 0 1 1 0 1 1 1 0 33 120 207 11 0 0 1 1 0 0 1 0 34 121 208 39 0 1 0 1 0 0 1 0 35 122 209 67 0 1 1 1 0 0 1 0 36 123 210 12 0 0 1 1 0 1 1 0 37 124 211 40 0 1 0 1 0 1 1 0 38 125 212 68 0 1 1 1 0 1 1 0 39 126 213 13 0 0 1 1 1 0 1 0 40 127 214 41 0 1 0 1 1 0 1 0 41 128 215 69 0 1 1 1 1 0 1 0 42 129 216 14 0 0 1 1 1 1 1 0 43 130 217 42 0 1 0 1 1 1 1 0 44 131 218 70 0 1 1 1 1 1 1 0 45 132 219 15 0 0 1 0 0 1 1 1 46 133 220 43 0 1 0 0 0 1 1 1 47 134 221 71 0 1 1 0 0 1 1 1 48 135 222 16 0 0 1 0 1 0 1 1 49 136 223 44 0 1 0 0 1 0 1 1 50 137 224 72 0 1 1 0 1 0 1 1 51 138 225 17 0 0 1 0 1 1 1 1 52 139 226 45 0 1 0 0 1 1 1 1 53 140 227 73 0 1 1 0 1 1 1 1 54 141 228 18 0 0 1 1 0 0 1 1 55 142 229 46 0 1 0 1 0 0 1 1 56 143 230 74 0 1 1 1 0 0 1 1 57 144 231 19 0 0 1 1 0 1 1 1 58 145 232 47 0 1 0 1 0 1 1 1 59 146 233 75 0 1 1 1 0 1 1 1 60 147 234 20 0 0 1 1 1 0 1 1 61 148 235 48 0 1 0 1 1 0 1 1 62 149 236 76 0 1 1 1 1 0 1 1 63 150 237 21 0 0 1 1 1 1 1 1 64 151 238 49 0 1 0 1 1 1 1 1 65 152 239 77 0 1 1 1 1 1 1 1 66 153 240 22 0 0 1 0 0 1 0 0 67 154 241 50 0 1 0 0 0 1 0 0 68 155 242 78 0 1 1 0 0 1 0 0 69 156 243 23 0 0 1 0 1 0 0 0 70 157 244 51 0 1 0 0 1 0 0 0 71 158 245 79 0 1 1 0 1 0 0 0 72 159 246 24 0 0 1 0 1 1 0 0 73 160 247 52 0 1 0 0 1 1 0 0 74 161 248 80 0 1 1 0 1 1 0 0 75 162 249 25 0 0 1 1 0 0 0 0 76 163 250 53 0 1 0 1 0 0 0 0 77 164 251 81 0 1 1 1 0 0 0 0 78 165 252 26 0 0 1 1 0 1 0 0 79 166 253 54 0 1 0 1 0 1 0 0 80 167 254 82 0 1 1 1 0 1 0 0 81 168 255 27 0 0 1 1 1 0 0 0 82 169 256 55 0 1 0 1 1 0 0 0 83 170 257 83 0 1 1 1 1 0 0 0 84 171 258 28 0 0 1 1 1 1 0 0 85 172 259 56 0 1 0 1 1 1 0 0 86 173 260 84 0 1 1 1 1 1 0 0 87 174 261 sts-1 #1, au-3 a sts-1 #2, au-3 b sts-1 #3, au-3 c
temx8 txc-04218 - 103 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 sts-3/au-3 vt2/tu-12 (2.048 mbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the 63 vt2/tu-12s into an sts-3/au-3 spe. each sts-3 carries three sts-1s. column 1 in each sts-1/au-3 is assigned to carry the path overhead bytes. sts-3/au-3 spe 1 2 3 36 12 3 5 35 vt vt vt vt 1 261 4 columns 14459 871 87 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 2 # 7 2 # 2 # 21 vt vt vt vt vt vt vt 2 # 2 # 2 # 2 # 2 # 2 # 2 # 42 2 # 30 29 66 1 vt2 3 r r r r r r r r r r r r r r r r r r 23 vt 2 # 87 vt 2 # 63 36 4 43 22 23 1 21 60 vt 2 # 15 1 21 11 45 67 36 bytes vt 2 # 44 vt 2 # note: columns 88, 89, 90, 175, 176 and 177 are fixed stuff.
temx8 txc-04218 - 104 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 sts-3/au-3 mapping (2.048 mbit/s) * note: columns 88, 89, 90, 175, 176 and 177 are fixed stuff. tu/ vt # vt/tu assignment registers 7 6 5 4 3 2 1 0 sts-3/au-3 column numbers* tu/ vt # vt/tu assignment registers 7 6 5 4 3 2 1 0 sts-3/au-3 column numbers* tu/ vt # vt/tu assignment registers 7 6 5 4 3 2 1 0 sts-3/au-3 column numbers* 1 0 0 0 0 0 0 0 no tu/vt selected 1 1 0 1 0 0 1 0 1 4, 67, 133, 199 22 1 1 0 0 0 1 0 1 5, 68, 134, 200 43 1 1 1 0 0 1 0 1 6, 69, 135, 201 2 1 0 1 0 1 0 0 1 7, 70, 136, 202 23 1 1 0 0 1 0 0 1 8, 71, 137, 203 44 1 1 1 0 1 0 0 1 9, 72, 138, 204 3 1 0 1 0 1 1 0 1 10, 73, 139, 205 24 1 1 0 0 1 1 0 1 11, 74, 140, 206 45 1 1 1 0 1 1 0 1 12, 75, 141, 207 4 1 0 1 1 0 0 0 1 13, 76, 142, 208 25 1 1 0 1 0 0 0 1 14, 77, 143, 209 46 1 1 1 1 0 0 0 1 15, 78, 144, 210 5 1 0 1 1 0 1 0 1 16, 79, 145, 211 26 1 1 0 1 0 1 0 1 17, 80, 146, 212 47 1 1 1 1 0 1 0 1 18, 81, 147, 213 6 1 0 1 1 1 0 0 1 19, 82, 148, 214 27 1 1 0 1 1 0 0 1 20, 83, 149, 215 48 1 1 1 1 1 0 0 1 21, 84, 150, 216 7 1 0 1 1 1 1 0 1 22, 85, 151, 217 28 1 1 0 1 1 1 0 1 23, 86, 152, 218 49 1 1 1 1 1 1 0 1 24, 87, 153, 219 8 1 0 1 0 0 1 1 0 25, 91, 154, 220 29 1 1 0 0 0 1 1 0 26, 92, 155, 221 50 1 1 1 0 0 1 1 0 27, 93, 156, 222 9 1 0 1 0 1 0 1 0 28, 94, 157, 223 30 1 1 0 0 1 0 1 0 29, 95, 158, 224 51 1 1 1 0 1 0 1 0 30, 96, 159, 225 10 1 0 1 0 1 1 1 0 31, 97, 160, 226 31 1 1 0 0 1 1 1 0 32, 98, 161, 227 52 1 1 1 0 1 1 1 0 33, 99, 162, 228 11 1 0 1 1 0 0 1 0 34, 100, 163, 229 32 1 1 0 1 0 0 1 0 35, 101, 164, 230 53 1 1 1 1 0 0 1 0 36, 102, 165, 231 12 1 0 1 1 0 1 1 0 37, 103, 166, 232 33 1 1 0 1 0 1 1 0 38, 104, 167, 233 54 1 1 1 1 0 1 1 0 39, 105, 168, 234 13 1 0 1 1 1 0 1 0 40, 106, 169, 235 34 1 1 0 1 1 0 1 0 41, 107, 170, 236 55 1 1 1 1 1 0 1 0 42, 108, 171, 237 14 1 0 1 1 1 1 1 0 43, 109, 172, 238 35 1 1 0 1 1 1 1 0 44, 110, 173, 239 56 1 1 1 1 1 1 1 0 45, 111, 174, 240 15 1 0 1 0 0 1 1 1 46, 112, 178, 241 36 1 1 0 0 0 1 1 1 47, 113, 179, 242 57 1 1 1 0 0 1 1 1 48, 114, 180, 243 16 1 0 1 0 1 0 1 1 49, 115, 181, 244 37 1 1 0 0 1 0 1 1 50, 116, 182, 245 58 1 1 1 0 1 0 1 1 51, 117, 183, 246 17 1 0 1 0 1 1 1 1 52, 118, 184, 247 38 1 1 0 0 1 1 1 1 53, 119, 185, 248 59 1 1 1 0 1 1 1 1 54, 120, 186, 249 18 1 0 1 1 0 0 1 1 55, 121, 187, 250 39 1 1 0 1 0 0 1 1 56, 122, 188, 251 60 1 1 1 1 0 0 1 1 57, 123, 189, 252 19 1 0 1 1 0 1 1 1 58, 124, 190, 253 40 1 1 0 1 0 1 1 1 59, 125, 191, 254 61 1 1 1 1 0 1 1 1 60, 126, 192, 255 20 1 0 1 1 1 0 1 1 61, 127, 193, 256 41 1 1 0 1 1 0 1 1 62, 128, 194, 257 62 1 1 1 1 1 0 1 1 63, 129, 195, 258 21 1 0 1 1 1 1 1 1 64, 130, 196, 259 42 1 1 0 1 1 1 1 1 65, 131, 197, 260 63 1 1 1 1 1 1 1 1 66, 132, 198, 261 sts-1 #1, au-3 a sts-1 #2, au-3 b sts-1 #3, au-3 c
temx8 txc-04218 - 105 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 stm-1/vc-4 tu-11 (1544 kbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the 84 tu-11s into an stm-1/vc-4. the temx8 per- mits the mapping of up to 8 t1 line signals into any of the 84 available time slots when the vc-4 is configured to carry tu-11s. 1 2 3 27 123 4 27 2 3 4 2 3 4 2 3 4 67 2 712 7 n p i n p i 7 n p i 1 p o h 1 261 3 columns tu-11 tug-2 tug-3 13159 86186 vc-4 86 1 11 11 3 7 1 1 10 4 stm-1/vc-4
temx8 txc-04218 - 106 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 stm-1 vc-4 mode (1.544 mbit/s) tu # vt/tu assignment registers 7 6 5 4 3 2 1 0 vc-4 column numbers tu # vt/tu assignment registers 7 6 5 4 3 2 1 0 vc-4 column numbers tu # vt/tu assignment registers 7 6 5 4 3 2 1 0 vc-4 column numbers 0 0 0 0 0 0 0 0 no tu selected 1 0 0 1 0 0 1 0 1 10 94 178 29 0 1 0 0 0 1 0 1 11 95 179 57 0 1 1 0 0 1 0 1 12 96 180 2 0 0 1 0 1 0 0 1 13 97 181 30 0 1 0 0 1 0 0 1 14 98 182 58 0 1 1 0 1 0 0 1 15 99 183 3 0 0 1 0 1 1 0 1 16 100 184 31 0 1 0 0 1 1 0 1 17 101 185 59 0 1 1 0 1 1 0 1 18 102 186 4 0 0 1 1 0 0 0 1 19 103 187 32 0 1 0 1 0 0 0 1 20 104 188 60 0 1 1 1 0 0 0 1 21 105 189 5 0 0 1 1 0 1 0 1 22 106 190 33 0 1 0 1 0 1 0 1 23 107 191 61 0 1 1 1 0 1 0 1 24 108 192 6 0 0 1 1 1 0 0 1 25 109 193 34 0 1 0 1 1 0 0 1 26 110 194 62 0 1 1 1 1 0 0 1 27 111 195 7 0 0 1 1 1 1 0 1 28 112 196 35 0 1 0 1 1 1 0 1 29 113 197 63 0 1 1 1 1 1 0 1 30 114 198 8 0 0 1 0 0 1 1 0 31 115 199 36 0 1 0 0 0 1 1 0 32 116 200 64 0 1 1 0 0 1 1 0 33 117 201 9 0 0 1 0 1 0 1 0 34 118 202 37 0 1 0 0 1 0 1 0 35 119 203 65 0 1 1 0 1 0 1 0 36 120 204 10 0 0 1 0 1 1 1 0 37 121 205 38 0 1 0 0 1 1 1 0 38 122 206 66 0 1 1 0 1 1 1 0 39 123 207 11 0 0 1 1 0 0 1 0 40 124 208 39 0 1 0 1 0 0 1 0 41 125 209 67 0 1 1 1 0 0 1 0 42 126 210 12 0 0 1 1 0 1 1 0 43 127 211 40 0 1 0 1 0 1 1 0 44 128 212 68 0 1 1 1 0 1 1 0 45 129 213 13 0 0 1 1 1 0 1 0 46 130 214 41 0 1 0 1 1 0 1 0 47 131 215 69 0 1 1 1 1 0 1 0 48 132 216 14 0 0 1 1 1 1 1 0 49 133 217 42 0 1 0 1 1 1 1 0 50 134 218 70 0 1 1 1 1 1 1 0 51 135 219 15 0 0 1 0 0 1 1 1 52 136 220 43 0 1 0 0 0 1 1 1 53 137 221 71 0 1 1 0 0 1 1 1 54 138 222 16 0 0 1 0 1 0 1 1 55 139 223 44 0 1 0 0 1 0 1 1 56 140 224 72 0 1 1 0 1 0 1 0 57 141 225 17 0 0 1 0 1 1 1 1 58 142 226 45 0 1 0 0 1 1 1 1 59 143 227 73 0 1 1 0 1 1 1 0 60 144 228 18 0 0 1 1 0 0 1 1 61 145 229 46 0 1 0 1 0 0 1 1 62 146 230 74 0 1 1 1 0 0 1 0 63 147 231 19 0 0 1 1 0 1 1 1 64 148 232 47 0 1 0 1 0 1 1 1 65 149 233 75 0 1 1 1 0 1 1 0 66 150 234 20 0 0 1 1 1 0 1 1 67 151 235 48 0 1 0 1 1 0 1 1 68 152 236 76 0 1 1 1 1 0 1 0 69 153 237 21 0 0 1 1 1 1 1 1 70 154 238 49 0 1 0 1 1 1 1 1 71 155 239 77 0 1 1 1 1 1 1 0 72 156 240 22 0 0 1 0 0 1 0 0 73 157 241 50 0 1 0 0 0 1 0 0 74 158 242 78 0 1 1 0 0 1 0 0 75 159 243 23 0 0 1 0 1 0 0 0 76 160 244 51 0 1 0 0 1 0 0 0 77 161 245 79 0 1 1 0 1 0 0 0 78 162 246 24 0 0 1 0 1 1 0 0 79 163 247 52 0 1 0 0 1 1 0 0 80 164 248 80 0 1 1 0 1 1 0 0 81 165 249 25 0 0 1 1 0 0 0 0 82 166 250 53 0 1 0 1 0 0 0 0 83 167 251 81 0 1 1 1 0 0 0 0 84 168 252 26 0 0 1 1 0 1 0 0 85 169 253 54 0 1 0 1 0 1 0 0 86 170 254 82 0 1 1 1 0 1 0 0 87 171 255 27 0 0 1 1 1 0 0 0 89 172 256 55 0 1 0 1 1 0 0 0 89 173 257 83 0 1 1 1 1 0 0 0 90 174 258 28 0 0 1 1 1 1 0 0 91 175 259 56 0 1 0 1 1 1 0 0 92 176 260 84 0 1 1 1 1 1 0 0 93 177 261 tug-3 a tug-3 b tug-3 c
temx8 txc-04218 - 107 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 stm-1/vc-4 tu-12 (2048 kbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the 63 tu-12s into an stm-1/vc-4. the temx8 per- mits the mapping of up to 8 e1 line signals into any of the 63 available time slots when the vc-4 is configured to carry tu-12s. 1 2 3 36 123 5 2 3 1 3 1 2 1 2 3 77717 14 15 p o h 1 261 4 columns tu-12 #1 tug-2 #1 16686186 vc-4 86 3 1 2 1 21 8 1 4 36 1 45 1 324 tug-3a tug-3b tug-3c stm-1/vc-4
temx8 txc-04218 - 108 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 stm-1 vc-4 mode (2048 kbit/s) tu # vt/tu assignment registers 7 6 5 4 3 2 1 0 vc-4 column numbers tu # vt/tu assignment registers 7 6 5 4 3 2 1 0 vc-4 column numbers tu # vt/tu assignment registers 7 6 5 4 3 2 1 0 vc-4 column numbers 1 0 0 0 0 0 0 0 no tu selected 1 1 0 1 0 0 1 0 1 10, 73, 136, 199 22 1 1 0 0 0 1 0 1 11, 74, 137, 200 43 1 1 1 0 0 1 0 1 12, 75, 138, 201 2 1 0 1 0 1 0 0 1 13, 76, 139, 202 23 1 1 0 0 1 0 0 1 14, 77, 140, 203 44 1 1 1 0 1 0 0 1 15, 78, 141, 204 3 1 0 1 0 1 1 0 1 16, 79, 142, 205 24 1 1 0 0 1 1 0 1 17, 80, 143, 206 45 1 1 1 0 1 1 0 1 18, 81, 144, 207 4 1 0 1 1 0 0 0 1 19, 82, 145, 208 25 1 1 0 1 0 0 0 1 20, 83, 146, 209 46 1 1 1 1 0 0 0 1 21, 84, 147, 210 5 1 0 1 1 0 1 0 1 22, 85, 148, 211 26 1 1 0 1 0 1 0 1 23, 86, 149, 212 47 1 1 1 1 0 1 0 1 24, 87, 150, 213 6 1 0 1 1 1 0 0 1 25, 88, 151, 214 27 1 1 0 1 1 0 0 1 26, 89, 152, 215 48 1 1 1 1 1 0 0 1 27, 90, 153, 216 7 1 0 1 1 1 1 0 1 28, 91, 154, 217 28 1 1 0 1 1 1 0 1 29, 92, 155, 218 49 1 1 1 1 1 1 0 1 30, 93, 156, 219 8 1 0 1 0 0 1 1 0 31, 94, 157, 220 29 1 1 0 0 0 1 1 0 32, 95, 158, 221 50 1 1 1 0 0 1 1 0 33, 96, 159, 222 9 1 0 1 0 1 0 1 0 34, 97, 160, 223 30 1 1 0 0 1 0 1 0 35, 98, 161, 224 51 1 1 1 0 1 0 1 0 36, 99, 162, 225 10 1 0 1 0 1 1 1 0 37, 100, 163, 226 31 1 1 0 0 1 1 1 0 38, 101, 164, 227 52 1 1 1 0 1 1 1 0 39, 102, 165, 228 11 1 0 1 1 0 0 1 0 40, 103, 166, 229 32 1 1 0 1 0 0 1 0 41, 104, 167, 230 53 1 1 1 1 0 0 1 0 42, 105, 168, 231 12 1 0 1 1 0 1 1 0 43, 106, 169, 232 33 1 1 0 1 0 1 1 0 44, 107, 170, 233 54 1 1 1 1 0 1 1 0 45, 108, 171, 234 13 1 0 1 1 1 0 1 0 46, 109, 172, 235 34 1 1 0 1 1 0 1 0 47, 110, 173, 236 55 1 1 1 1 1 0 1 0 48, 111, 174, 237 14 1 0 1 1 1 1 1 0 49, 112, 175, 238 35 1 1 0 1 1 1 1 0 50, 113, 176, 239 56 1 1 1 1 1 1 1 0 51, 114, 177, 240 15 1 0 1 0 0 1 1 1 52, 115, 178, 241 36 1 1 0 0 0 1 1 1 53, 116, 179, 242 57 1 1 1 0 0 1 1 1 54, 117, 180, 243 16 1 0 1 0 1 0 1 1 55, 118, 181, 244 37 1 1 0 0 1 0 1 1 56, 119, 182, 245 58 1 1 1 0 1 0 1 1 57, 120, 183, 246 17 1 0 1 0 1 1 1 1 58, 121, 184, 247 38 1 1 0 0 1 1 1 1 59, 122, 185, 248 59 1 1 1 0 1 1 1 1 60, 123, 186, 249 18 1 0 1 1 0 0 1 1 61, 124, 187, 250 39 1 1 0 1 0 0 1 1 62, 125, 188, 251 60 1 1 1 1 0 0 1 1 63, 126, 189, 252 19 1 0 1 1 0 1 1 1 64, 127, 190, 253 40 1 1 0 1 0 1 1 1 65, 128, 191, 254 61 1 1 1 1 0 1 1 1 66, 129, 192, 255 20 1 0 1 1 1 0 1 1 67, 130, 193, 256 41 1 1 0 1 1 0 1 1 68, 131, 194, 257 62 1 1 1 1 1 0 1 1 69, 132, 195, 258 21 1 0 1 1 1 1 1 1 70, 133, 196, 259 42 1 1 0 1 1 1 1 1 71, 134, 197, 260 63 1 1 1 1 1 1 1 1 72, 135, 198, 261
temx8 txc-04218 - 109 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 memory map the temx8 mapper memory map consists of control bits, status indications, and counters which may be accessed by the microprocessor. the memory map segment consists of those functions which are common to all channels and per channel address locations. the address field for the temx8 consists of 15 bits (a14 -a0). address bits a14-a10 are used to access a page, while address bits a9-a0 define functions within the page. address locations within the range of 00+000h to 00+094h are allocated for common device functions for all channels. address locations between 095h and 3ffh are unassigned. address locations between x+000h and x+20bh are allocated for each of the 8 channels. address locations between x+21bh and x+3ffh are unassigned, where x is equal to 01h for channel 1 and 08h for channel 8. x equals 00h for the temx8 common functions. address locations for x equal to 09h and 1fh are unas- signed. unassigned address locations should not be accessed by the microprocessor. unused bit positions within a register location may contain unspecified values when read, unless a 0 or 1 value is indicated in the tables below. unused address locations can be written to by the microprocessor, in which case the unused bit positions must always be set to 0 unless otherwise noted. counters other then the one second performance counters may be configured to roll over, or saturating. when the counters are configured as roll-over, a counter will roll-over to the value of 1 on the next count after the counter reaches its maximum value. when the counters are configured to be saturation, a counter that is read by the microprocessor will clear. all counters within the temx8 will be cleared when a 1 is written to control bit resetc (bit 5, 01ah). the low byte (bits 7-0) of a 16 bit counter should be read first immediately followed by reading the high byte (bits 15-8). during a read cycle, counts that occur during the read cycle will be held until the completion of the read cycle. except for the tandem connection feature, current and previous one second counters are provided. the counters are disabled when the one second pulse is not provided. the current one second counters, and previous one counters are updated at one second intervals by the rising edge of the externally generated one second pulse. all alarm bits have the following status bit locations: unlatched, latched, one second, and previous one second indications. a latched alarm bit position is reset on a microprocessor read cycle. the one second, and previous one second alarm bit positions are disabled when the one second pulse is not provided. an alarm bit latches on a positive transition, negative transition, or a positive or negative transition. all the register status fields will use the following notations: r=read; r(l)=read (latched); r/w=read/write; or w=write. device id address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000r11010111 001r11100000 002r00000111 003 r revision (version) level 0 0 0 1 004 r set to 0000 set to 0000
temx8 txc-04218 - 110 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 common control registers - a and b sides mask bits for bus a and b status alarms address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 006 r/w reseth 00b to 017 reserved 018 r/w prbsa prbsg 019 r/w clpbk dv1sel pddo dbpe 01a r/w resetc block sts3 crov 01b r/w intr1 intr0 ptalte v5al10 01c reserved 01d r/w tctae j2aisen plsaise uqaise uaise se1ais heaise 01e r/w vcaise dlcae tcuae tcaise 01f r/w vctce dlcte j2tce plstce uqtce ustce 020 r/w vcrdie dlcre psrdie j2rdie uqrdie urdie 0111 to 038 reserved 039 r/w dreset 03a r/w tjust pado abpe tobwz bahze aahze addi 03b r/w tb2dis abod thrsby 03c r/w treset address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 005 r/w hint mgda mgdb mgab mpcda mpcdb mpcab 007 r/w mdvcai s mduneq mdrdic mdrdip mdrdis mdsler mdrfi 008 r/w mdrffe mdais mdlop mdndf mdsize 009 r/w mtais mtffe mool mtlos mtloc mdj2tim mdj2lol 00a r/w mtclm mtcll mtctm mtcais mtcuq mtcrdi mtcodi 03d r/w reserved mbbloc mabloc 03e reserved 03f r/w channel polling register (channels 8-1) add alarm mask bits 040 r/w reserved 041 r/w reserved
temx8 txc-04218 - 111 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 bus a and b common status alarms mask bits for bus a drop alarms 042 r/w reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 050 r gda gdb gab pcda pcdb pcab 051 r bbloc abloc 052 r(l) lbbloc labloc 053 r pbbloc pabloc 054 r fbbloc fabloc 055 r channel polling register (channels 8-1) add alarm bits 056 r reserved 057 r reserved 058 r reserved 059 r reserved resetd 05a to 05f r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 043 r/w ma3uais ma2uais ma1uais madpar madloc 044 r/w ma3oom ma2oom ma1oom ma3lom ma2lom ma1lom 045 r/w channel polling register (channels 8-1) a bus drop alarm mask bits 046 r/w reserved 047 r/w reserved 048 r/w reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
temx8 txc-04218 - 112 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 a drop bus status registers and toh registers mask bits for bus b drop alarms address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 060 r a3uais a2uais a1uais adpar adloc 061 r a3hoom a2hoom a1hoom a3hlom a2hlom a1hlom 062 r(l) la3uais la2uais la1uais ladpar ladloc 063 r(l) la3hoom la2hoom la1hoom la3hlom la2hlom la1hlom 064 r pa3uais pa2uais pa1uais padpar padloc 065 r pa3hoom pa2hoom pa1hoom pa3hlom pa2hlom pa1hlom 066 r fa3uais fa2uais fa1uais fadpar fadloc 067 r fa3hoom fa2hoom fa1hoom fa3hlom fa2hlom fa1hlom 068 r a side drop bus h1 pointer byte (sts-3 sts-1 no. 1, stm-1 vc-4) 069 r a side drop bus h1 pointer byte (sts-3 sts-1 no. 2) 06a r a side drop bus h1 pointer byte (sts-3 sts-1 no. 3) 06b r a side drop bus h2 pointer byte (sts-3 sts-1 no. 1, stm-1 vc-4) 06c r a side drop bus h2 pointer byte (sts-3 sts-1 no. 2) 06d r a side drop bus h2 pointer byte (sts-3 sts-1 no. 3) 06e r a side drop bus h4 overhead byte (sts-3 sts-1 no. 1, stm-1 vc-4) 06f r a side drop bus h4 overhead byte (sts-3 sts-1 no. 2) 070 r a side drop bus h4 overhead byte (sts-3 sts-1 no. 3) 071 r a side drop bus e1 overhead byte (sts-3 sts-1 no. 1, stm-1 vc-4) 072 r a side drop bus e1 overhead byte (sts-3 sts-1 no. 2) 073 r a side drop bus e1 overhead byte (sts-3 sts-1 no. 3) 074 r a side drop channel polling register (channels 8-1) alarm bits 075 r reserved 076 r reserved 077 r reserved 078 to 07f r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 049 r/w mb3uais mb2uais mb1uais mbdpar mbdloc 04a r/w mb3oom mb2oom mb1oom mb3lom mb2lom mb1lom 04b r/w channel polling register (channels 8-1) b bus drop alarm mask bits
temx8 txc-04218 - 113 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 b drop bus status registers and toh registers 04c r/w reserved 04d r/w reserved 04e r/w reserved 04f r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 080 r b3uais b2uais b1uais bdpar bdloc 081 r b3hoom b2hoom b1hoom b3hlom b2hlom b1hlom 082 r(l) lb3uais lb2uais lb1uais lbdpar lbdloc 083 r(l) lb3hoom lb2hoom lb1hoom lb3hlom lb2hlom lb1hlom 084 r pb3uais pb2uais pb1uais pbdpar pbdloc 085 r pb3hoom pb2hoom pb1hoom pb3hlom pb2hlom pb1hlom 086 r fb3uais fb2uais fb1uais fbdpar fbdloc 087 r fb3hoom fb2hoom fb1hoom fb3hlom fb2hlom fb1hlom 088 r b side drop bus h1 pointer byte (sts-3 sts-1 no. 1, stm-1 vc-4) 089 r b side drop bus h1 pointer byte (sts-3 sts-1 no. 2) 08a r b side drop bus h1 pointer byte (sts-3 sts-1 no. 3) 08b r b side drop bus h2 pointer byte (sts-3 sts-1 no. 1, stm-1 vc-4) 08c r b side drop bus h2 pointer byte (sts-3 sts-1 no. 2) 08d r b side drop bus h2 pointer byte (sts-3 sts-1 no. 3) 08e r b side drop bus h4 overhead byte (sts-3 sts-1 no. 1, stm-1 vc-4) 08f r b side drop bus h4 overhead byte (sts-3 sts-1 no. 2) 090 r b side drop bus h4 overhead byte (sts-3 sts-1 no. 3) 091 r b side drop bus e1 overhead byte (sts-3 sts-1 no. 1, stm-1 vc-4) 092 r b side drop bus e1 overhead byte (sts-3 sts-1 no. 2) 093 r b side drop bus e1 overhead byte (sts-3 sts-1 no. 3) 094 r b side drop channel polling register (channels 8-1) alarm bits 095 r reserved 096 r reserved 097 r reserved 098 to 33f r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
temx8 txc-04218 - 114 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a and b drop and add side control registers (n = 1 to 8) channel n - a side control registers (n = 1 to 8) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+000 r/w rnnrzp rnclki rnb8zs rnlais x+001 reserved x+002 r/w tnlint1-0 tnnrzp tne1sl tnclki tnb8zs tnsais tnaise x+003 r/w exnlos exnlosp x+004 r/w tnptg tnanz tnprn lnlbk fnlbk x+006 r/w rnlint1-0 rnoutl rne1sl fnrdis rnsel tnsel1 tnsel0 x+007 r/w tnvtvc tndisb x+008 r/w rnvtvc rndien tcnre rnaise rnsais x+009 r/w tnreset x+00a to x+00f r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+010 r/w arntcen arnsl(1-3) arnj2s1 arnj2s0 x+011 r/w dachnr x+012 r/w a side drop bus channel n vt/tu selection x+019 r reserved x+01a r/w a side add bus channel n vt/tu selection x+01b r reserved x+01c to x+05b r/w a side add bus channel n j2 byte 64 byte message or a side add bus channel n j2 byte 16 byte message (01ch - 02bh) unused - 16 bytes (02ch - 03bh) a side add bus channel n n2 byte 16 byte message (03ch - 04bh) unused - 16 bytes (04ch - 05bh) x+05c r/w a side add bus channel n v1 byte x+05d r/w a side add bus channel n v2 byte x+05e r/w a side add bus channel n v4 byte x+05f r/w a side add bus channel n o bits x+060 r/w a side add bus channel n v5 byte x+061 r/w a side add bus channel n n2 byte x+062 r/w a side add bus channel n k4 byte x+063 r/w atntcais atngais atntptv anuqge anuqsu atntcen atnj2ten atnj2tsz
temx8 txc-04218 - 115 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side drop pointer leak registers (n = 1 to 8) channel n - b side control registers (n = 1 to 8) x+064 r/w atnrfi atnrdip atnrdic atnrdis atnfb2 atnt- cuq atnv5bs x+065 r/w atnffb atnsl(1-3) atnk4pc anhighz x+066 r/w atntcso atntcsr atnv4bs x+067 to x+07f r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+017 r/w pointer leak value (bit 7-0) x+018 r/w reserved pointer leak value (bit 9-8) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+080 r/w brntcen brnsl(1-3) brnj2s1 brnj2s0 x+081 r/w dbchnr x+082 r/w b side drop bus channel n vt/tu selection x+08a r/w b side add bus channel n vt/tu selection x+08b reserved x+08c to x+0cb r/w b side add bus channel n j2 byte 64 byte message or b side add bus channel n j2 byte 16 byte message (0bch - 09bh) unused - 16 bytes (09ch - 0abh) b side add bus channel n n2 byte 16 byte message (0ach - 0bbh) unused - 16 bytes (0bch - 0cbh) x+0cc r/w b side add bus channel n v1 byte x+0cd r/w b side add bus channel n v2 byte x+0ce r/w b side add bus channel n v4 byte x+0cf r/w b side add bus channel n o bits x+0d0 r/w b side add bus channel n v5 byte x+0d1 r/w b side add bus channel n n2 byte x+0d2 r/w b side add bus channel n k4 byte x+0d3 r/w btntcais btngais btntptv bnuqge bnuqsu btntcen btnj2ten btnj2tsz x+0d4 r/w btnrfi btnrdip btnrdic btnrdis btnfb2 btntcuq btnv5bs address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
temx8 txc-04218 - 116 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop pointer leak registers (n = 1 to 8) channel n - a and b side add alarm mask bit registers (n = 1 to 8) channel n - a and b side add alarm and counter registers (n = 1 to 8) x+0d5 r/w btnffb btnsl(1-3) btnk4pc bnhighz x+0d6 r/w btntcso btntcsr btnv4bs x+0d7 to x+0ff r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+087 r/w pointer leak value (bit 7-0) x+088 r/w reserved pointer leak value (bit 9-8) x+089 r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+005 r/w mntais mnbtfe mnatfe mnool mntlos mntloc address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+100 r tnais tbnffe tanffe cnool tnlos tnloc x+101 r(l) ltnais ltbnffe ltanffe lcnool ltnlos ltnloc x+102 reserved x+103 r ptnais ptbnffe ptanffe pcnool ptnlos ptnloc x+104 r ftnais ftbnffe ftanffe fcnool ftnlos ftnloc x+105 r/w code violation counter - low order byte (7-0) x+106 r/w code violation counter - low order byte (15-8) x+107 r/w previous one second code violation counter - low order byte (7-0) x+108 r/w previous one second code violation counter - low order byte (15-8) x+109 r/w current one second code violation counter - low order byte (7-0) x+10a r/w current one second code violation counter - low order byte (15-8) x+10b to x+10f r reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
temx8 txc-04218 - 117 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side drop alarm mask bit registers (n = 1 to 8) channel n - a side drop status registers (n = 1 to 8) channel n - a side drop counters (n = 1 to 8) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+013 r/w manvais manuqe manrdic manrdip manrdis mansler manrfi x+014 r/w manrfe manais manlop manndf mansize x+015 r/w manj2tim manj2lol x+016 r/w mantclm mantcll mantctm mantcais mantcuq mantcrdi mantcodi address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+110 r anvcais anuneq anrdic anrdip anrdis ansler anrfi x+111 r anrffe anais anlop anndf ansize x+112 r anj2tim anj2lol x+113 r antclm antcll antctm antcais antcuq antcrdi antcodi x+114 r(l) lanvcais lanuneq lanrdic lanrdip lanrdis lansler lanrfi x+115 r(l) lanrffe lanais lanlop lanndf lansize x+116 r(l) lanj2tim lanj2lol x+117 r(l) lantclm lantcll lantctm lantcais lantcuq lantcrdi lantcodi x+118 r panvcais panuneq panrdic panrdip panrdis pansler panrfi x+119 r panrffe panais panlop panndf pansize x+11a r panj2tim panj2lol x+11b r pantclm pantcll pantctm pantcais pantcuq pantcrdi pantcodi x+11c r fanvcais fanuneq fanrdic fanrdip fanrdis fansler fanrfi x+11d r fanrffe fanais fanlop fanndf fansize x+11e r fanj2tim fanj2lol x+11f r fantclm fantcll fantctm fantcais fantcuq fantcrdi fantcodi address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+120 r/w a side positive justification counter for channel n - 8 bits x+121 r/w a side negative justification counter for channel n - 8 bits x+122 r/w a side rei (v5 byte) counter for channel n - 8 bits x+123 r/w a side bip-2 (v5 byte) counter for channel n - 8 bits x+124 r/w a side tc oei (n2 byte) counter for channel n - 8 bits x+125 r/w a side tc rei (n2 byte) counter for channel n - 8 bits
temx8 txc-04218 - 118 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side drop overhead byte registers (n = 1 to 8) x+126 r/w a side tc bip-2 (n2 byte) counter for channel n - 8 bits x+127 r a side previous one second pj counter for channel n - low order count (7-0) x+128 r a side previous one second pj counter for channel n - high order count (15-8) x+129 r a side previous one second nj counter for channel n - low order count (7-0) x+12a r a side previous one second nj counter for channel n - high order count (15-8) x+12b r a side previous one second rei counter for channel n - low order count (7-0) x+12c r a side previous one second rei counter for channel n - high order count (15-8) x+12d r a side previous one second bip-2 counter for channel n - low order count (7-0) x+12e r a side previous one second bip-2 counter for channel n - high order count (15-8) x+12f to x+134 reserved x+135 r a side current one second pj counter for channel n - low order count (7-0) x+136 r a side current one second pj counter for channel n - high order count (15-8) x+137 r a side current one second nj counter for channel n - low order count (7-0) x+138 r a side current one second nj counter for channel n - high order count (15-8) x+139 r a side current one second rei counter for channel n - low order count (7-0) x+13a r a side current one second rei counter for channel n - high order count (15-8) x+13b r a side current one second bip-2 counter for channel n - low order count (7-0) x+13c r a side current one second bip-2 counter for channel n - high order count (15-8) x+13d to x+142 reserved x+20c to x+3ff reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+143 to x+162 r a side drop bus channel n j2 byte 64 byte message or a side drop bus channel n j2 byte 16 byte message a side drop bus channel n n2 byte 16 byte message a side channel n microprocessor written 16 byte message a side channel n microprocessor written 16 byte message x+163 to x+182 r/w x+183 r a side drop bus channel n v1 byte x+184 r a side drop bus channel n v2 byte address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
temx8 txc-04218 - 119 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop alarm mask bit registers (n = 1 to 8) channel n - b side drop status registers (n = 1 to 8) x+185 r a side drop bus channel n v4 byte x+186 r a side drop bus channel n v5 byte x+187 r a side drop bus channel n j2 byte x+188 r a side drop bus channel n n2 byte x+189 r a side drop bus channel n k4 byte x+18a r a side drop bus channel n o bits x+18b reserved address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+083 r/w mbnvais mbnuqe mbnrdic mbnrdip mbnrdis mbnsler mbnrfi x+084 r/w mbnrfe mbnais mbnlop mbnndf mbnsize x+085 r/w mbnj2tim mbnj2lol x+086 r/w mbntclm mbntcll mbntctm mbntcais mbntcuq mbntcrdi mbntcodi address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+190 r bnvcais bnuneq bnrdic bnrdip bnrdis bnsler bnrfi x+191 r bnrffe bnais bnlop bnndf bnsize x+192 r bnj2tim bnj2lol x+193 r bntclm bntcll bntctm bntcais bntcuq bntcrdi bntcodi x+194 r(l) lbnvcais lbnuneq lbnrdic lbnrdip lbnrdis lbnsler lbnrfi x+195 r(l) lbnrffe lbnais lbnlop lbnndf lbnsize x+196 r(l) lbnj2tim lbnj2lol x+197 r(l) lbntclm lbntcll lbntctm lbntcais lbntcuq lbntcrdi lbntcodi x+198 r pbnvcais pbnuneq pbnrdic pbnrdip pbnrdis pbnsler pbnrfi x+199 r pbnrffe pbnais pbnlop pbnndf pbnsize x+19a r pbnj2tim pbnj2lol x+19b r pbntclm pbntcll pbntctm pbntcais pbntcuq pbntcrdi pbntcodi x+19c r fbnvcais fbnuneq fbnrdic fbnrdip fbnrdis fbnsler fbnrfi x+19d r fbnrffe fbnais fbnlop fbnndf fbnsize x+19e r fbnj2tim fbnj2lol x+19f r fbntclm fbntcll fbntctm fbntcais fbntcuq fbntcrdi fbntcodi address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
temx8 txc-04218 - 120 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop counters (n = 1 to 8) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+1a0 r/w b side positive justification counter for channel n - 8 bits x+1a1 r/w b side negative justification counter for channel n - 8 bits x+1a2 r/w b side rei (v5 byte) counter for channel n - 8 bits x+1a3 r/w b side bip-2 (v5 byte) counter for channel n - 8 bits x+1a4 r/w b side tc oei (n2 byte) counter for channel n - 8 bits x+1a5 r/w b side tc rei (n2 byte) counter for channel n - 8 bits x+1a6 r/w b side tc bip-2 (n2 byte) counter for channel n - 8 bits x+1a7 r b side previous one second pj counter for channel n - low order count (7-0) x+1a8 r b side previous one second pj counter for channel n - high order count (15-8) x+1a9 r b side previous one second nj counter for channel n - low order count (7-0) x+1aa r b side previous one second nj counter for channel n - high order count (15-8) x+1ab r b side previous one second rei counter for channel n - low order count (7-0) x+1ac r b side previous one second rei counter for channel n - high order count (15-8) x+1ad r b side previous one second bip-2 counter for channel n - low order count (7-0) x+1ae r b side previous one second bip-2 counter for channel n - high order count (15-8) x+1af to x+1b4 reserved x+1b5 r b side current one second pj counter for channel n - low order count (7-0) x+1b6 r b side current one second pj counter for channel n - high order count (15-8) x+1b7 r b side current one second nj counter for channel n - low order count (7-0) x+1b8 r b side current one second nj counter for channel n - high order count (15-8) x+1b9 r b side current one second rei counter for channel n - low order count (7-0) x+1ba r b side current one second rei counter for channel n - high order count (15-8) x+1bb r b side current one second bip-2 counter for channel n - low order count (7-0) x+1bc r b side current one second bip-2 counter for channel n - high order count (15-8) x+1bd to x+1c2 reserved
temx8 txc-04218 - 121 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop overhead byte registers (n = 1 to 8) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+1c3 to x+1e2 r b side drop bus channel n j2 byte 64 byte message or b side drop bus channel n j2 byte 16 byte message b side drop bus channel n n2 byte 16 byte message b side channel n microprocessor written 16 byte message b side channel n microprocessor written 16 byte message x+1e3 to x+202 r/w x+203 r b side drop bus channel n v1 byte x+204 r b side drop bus channel n v2 byte x+205 r b side drop bus channel n v4 byte x+206 r b side drop bus channel n v5 byte x+207 r b side drop bus channel n j2 byte x+208 r b side drop bus channel n n2 byte x+209 r b side drop bus channel n k4 byte x+20a r b side drop bus channel n o bits x+20b reserved
temx8 txc-04218 - 122 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 memory map descriptions manufacturer and device identification description the manufacturer and device identification are based on the field format given in ieee standard 1149.1 on boundary scan, and the id assigned by the solid state products engineering council (jedec) to the transwitch corporation. the serial format for this id, which is located in registers 000h through 003h, is shown below. bit 7 in register 003h is at the left and bit 0 of register 000h is at the right: the manufacturer id assigned for transwitch devices is defined as 107 decimal, located in bits 7 through 1 (lsb) of register 000h, and bits 3 (msb) through 0 of register 001h. the part number of the temx8 is 04222, which is expressed as a binary number in bits 7 through 4 (lsb) in register 001h, bits 7 through 0 in 002h, and bits 3 (msb) through 0 in 003h. the revision field occupies bits 7 through 4 (lsb) in register 003h. the regis- ters at address 004h is a read/write locations that is reserved for future use. a and b side common control registers - descriptions msb lsb revision part number manufacturer identifier 1 4 bits 16 bits 11 bits address bit symbol description 006 7-1 not used: 0 reseth reset device: this bit is equivalent to the hardware reset. when a 1 is written to this bit, the internal fifos and logic are reset to preset values, counters and control bits in the memory map are reset to zero. this bit is self clearing. four microseconds after this bit is written with a 1, status bit resetd (bit 0, register 059h) transitions to a 1. this transition indi- cates that the reset operation is complete and microprocessor access of the device can begin. 018 7-4 not used: 3prbsa test analyzer add/drop direction: when a 0 is written into this bit, the prbs test analyzer for all channels are configured to be in the receive direction. writing a 1 to this bit configures the prbs analyzers to be in the transmit direction. 2 not used: 1prbsg test generator add/drop direction: when a 0 is written into this bit, the prbs test generators for all channels are configured to be in the transmit direction. writing a 1 to this bit configures the prbs generators to be in the receive direction. 0 not used:
temx8 txc-04218 - 123 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 019 7-5 not used: 4clpbk combus sonet/sdh local loopback: a 1 written to this bit will enable a combus sonet/sdh loopback. this loopback is valid for either the drop bus or add bus timing modes, and only when control bit dv1sel (bit 2 below) is set to 1. when this loopback is enabled, the drop buses are inhibited from passing vt/tu to the demapper. vt/tu are mapped and demapped according to the vt/tu add and drop selec- tion registers. 3 not used: 2 dv1sel drop bus v1 reference enable: common control bit for both the a and b drop buses. when set to 0, bits 7 and 8 in the h4 byte are monitored for the multiframe indication to determine the v1 byte location for all vt/tus. when set to 1, the v1 pulse in the c1j1v1 signal carries the v1 byte location for all channels. a drop bus reset operation should be performed after modifying this bit. see dreset bit at address 039h. 1 pddo a/b drop bus parity detected on data only: common control bit for both drop buses. a 1 causes parity to be calculated over the data byte only. a 0 causes parity to be calculated over the data byte, spe and c1j1v1 signals. please refer to the table provided below for dbpe con- trol bit. 0dbpe a/b drop bus even parity detected: this bit works in conjunction with the control bit pddo above to determine the parity calculation in the drop direction. dbpe pddo action (for both a and b drop buses) 0 0 odd parity check over drop data, spe, and c1j1v1. 0 1 odd parity check over drop data only. 1 0 even parity check over drop data, spe, and c1j1v1. 1 1 even parity check over drop data only. other than reporting the event, no action is taken upon parity error indi- cation. address bit symbol description
temx8 txc-04218 - 124 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 01a 7-6 not used: 5 resetc reset all channel counters. a 1 written to this control bit causes all performance counters to be reset to a zero value (for saturating counters) or the fe/fffe hex values (for 8/16-bit non-saturating counters). 4block block count: a 1 enables two bip-2 errors in the v5 byte and the n2 tandem connection byte to be counted as a single error (block) for all performance counters. a 0 enables two bip-2 errors to be counted as two errors. 3-2 not used: 1sts3 sts-3 mode selection: the temx8 sdh/sonet operating modes are according to the table below. a drop bus reset operation should be per- formed after modifying this bit. see dreset bit at address 039 sts3 format selected 1 sts-3 (stm-1 au-3) format 0 stm-1 au-4 (sts-3c) format 0crov counters roll-over enable: a 0 configures all counters to be saturat- ing unless otherwise noted. that is, all counters will stop at their speci- fied maximum count value. a microprocessor read cycle will clear a saturating counter. a 1 configures all counters to function in the roll-over mode. that is, when the maximum count is reached in a counter, the next count causes it to roll over and start at a count of 0. a microproces- sor read cycle does not clear a counter when the counters are config- ured in the roll-over mode. upon power-up, this control bit is set to 0 (saturation mode). the counter will preset to the value feh for 8-bit counters or the value fffeh for 16-bit counters, when this control bit is set to 1, followed by writing a 1 to control bit resetc (bit 5, 01ah). these are values selected to ensure that a roll-over occurs after a few counts. 01b 7 6 intr1 intr0 interrupt/latched alarm positive/negative transition selection: an alarm will latch according to the alarm transitions given in the table below. intr1 intr0 action 0 0 no event or interrupt indication 1 0 latch on positive alarm transition 0 1 latch on negative alarm transition 1 1 latch on both positive and negative alarm transitions 5-2 not used: 1ptalte pointer tracking ais to lop transition enabled: a 1 enables the ais to lop transition in each of the pointer tracking state machines. a 0 will disables this transition. 0v5al10 v5 alarm detection select 10: a 1 selects 10 consecutive rdi asser- tions for detection and recovery for all channels. a 0 selects 5 consecu- tive rdi assertions for detection and recovery. the selection is valid for both three bit rdi and single bit rdi. address bit symbol description
temx8 txc-04218 - 125 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 01d 7 tctae tandem connection loss of lock, mismatch, loss of multiframe alarms line ais enable: a common control bit for both the a and b drop bus tandem connection loss of lock (a/bntcll), tandem con- nection mismatch (a/bntctm), and tandem connection loss of multi- frame (a/bllm) alarms. a 1 enables any of these alarms for the active bus to generate line ais provided control bit rnaise is set to 1. 6j2aisen j2 alarm line ais enable: a common control for both the a and b drop bus j2 alarms. a 1 enables a j2 loss of lock (a/bnj2lol) or j2 trace mismatch (a/bj2tim) alarm for the active bus to generate line ais provided control bit rnaise is set to 1. 5plsaise path label alarm line ais enable: a common control for both the a and b drop bus path signal alarm (a/bnsler). a 1 enables a path sig- nal label mismatch alarm for the active bus to generate line ais provided control bit rnaise is set to 1. 4uqaise unequipped line ais enable: a common control for both the a and b drop bus unequipped path signal alarm (a/bnuneq). a 1 enables a unequipped alarm for the active bus to generate line ais provided con- trol bit rnaise is set to 1. 3 not used: 2uaise upstream ais alarm line ais enable: a common control for both the a and b drop bus upstream ais alarm (a/bxuais). a 1 enables an upstream ais alarm for the active bus to generate line ais provided con- trol bit rnaise is set to 1. where x is equaled to the numbered sts-1 in the sts-3. 1se1ais select e1ais: works in conjunction with the heaise control bit described below. the heaise bit must be set to 1 in order for this con- trol bit to function. a 1 enables the toh e1 byte ais detection circuit. a 0 enables the toh h1/h2 byte ais detection circuit. 0heaise a/b h1/h2 or e1 byte ais enable: works in conjunction with the se1ais control bit described above. common control for both the a and b drop buses. a 1 enables ais detection in either the sdh/sonet h1/h2 bytes (control bit se1ais is 0), or in the e1 bytes (control bit se1ais is 1). a 0 disables the detection of an upstream ais state. note that the tu/vt pointer tracking state machine ais detection circuitry operates independently of h1/h2 or e1 byte ais detection circuits. address bit symbol description
temx8 txc-04218 - 126 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 01e 7-4 not used: 3vcaise vc ais alarm line ais enable: a common control for both the a and b drop bus signal label ais alarm (a/bnvcais). a 1 enables a vc ais alarm for the active bus to generate line ais provided control bit rnaise is set to 1. 2dlcae drop bus loss of clock alarm line ais enable: a common control for both the a and b drop bus upstream ais alarm (a/bdloc). a 1 enables a drop bus loss of clock alarm for the active bus to generate line ais provided control bit rnaise is set to 1. 1 tcuae tandem connection unequipped alarm line ais enable: a common control for both the a and b drop bus tandem connection unequipped alarm (a/bntcuq). a 1 enables an tandem connection unequipped alarm for the active bus to generate line ais provided control bit rnaise is set to 1. 0tcaise tandem connection ais alarm line ais enable: a common control for both the a and b drop bus tandem connection ais alarm (a/bntcais). a 1 enables an tandem connection ais alarm for the active bus to generate line ais provided control bit rnaise is set to 1. address bit symbol description
temx8 txc-04218 - 127 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 01f 7 not used: 6 vctce vc ais alarm tandem connection rdi/odi enable: a common con- trol for both the a and b drop bus signal label ais alarm (a/bnvcais). a 1 enables a vc ais alarm for the active bus to generate a tandem con- nection rdi and odi provided control bit tcnreis set to 1, and the tan- dem connection feature is enabled. 5dlcte drop bus loss of clock alarm tandem connection rdi/odi enable: a common control for both the a and b drop bus loss of clock alarm (a/bdloc). a 1 enables a drop bus loss of clock alarm for the active bus to generate a tandem connection rdi and odi provided con- trol bit tcnre is set to 1, and the tandem connection feature is enabled. 4j2tce j2 alarm tandem connection rdi/odi enable: a common control for both the a and b drop bus j2 alarms. a 1 enables a j2 loss of lock (a/bnj2lol) or j2 trace mismatch (a/bnj2tim) alarm for the active bus to generate a tandem connection rdi and odi provided control bit tcnre is set to 1, and the tandem connection feature is enabled. 3plstce path label alarm tandem connection rdi/odi enable: a common control for both the a and b drop bus path signal alarm (a/bnsler). a 1 enables a path signal label mismatch alarm for the active bus to gener- ate a tandem connection rdi and odi provided control bit tcnre is set to 1, and the tandem connection feature is enabled. 2uqtce unequipped alarm tandem connection rdi/odi enable: a common control for both the a and b drop bus unequipped alarm (a/bnuneq). a 1 enables a unequipped alarm for the active bus to generate a tandem connection rdi and odi provided control bit tcnre is set to 1, and the tandem connection feature is enabled. 1 not used: 0ustce upstream ais alarm tandem connection rdi/odi enable: a com- mon control for both the a and b drop bus upstream ais alarm (a/bxuais). a 1 enables an upstream ais alarm for the active bus to generate a tandem connection rdi and odi provided control bit tcnre is set to 1, and the tandem connection feature is enabled. address bit symbol description
temx8 txc-04218 - 128 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 020 7 not used: 6 vcrdie vc ais alarm rdi enable: a common control for both the a and b drop bus signal label ais alarm (a/bnvcais). a 1 enables a vc ais alarm for the active bus to generate either a single bit rdi state or a remote server defect indication (three bit rdi) when control bit rndien is set to 1. 5 dlcre drop bus loss of clock rdi enable: a common control for both the a and b drop bus loss of clock alarm (a/bdloc). a 1 enables a drop bus loss of clock alarm for the active bus to generate either a single bit rdi state or a remote server defect indication (three bit rdi) when control bit rndien is set to 1. 4 psrdie path label alarm rdi enable: a common control for both the a and b drop bus path signal alarm (a/bnsler). a 1 enables a path signal label mismatch alarm for the active bus to generate a remote payload defect indication (three bit rdi) when control bit rndien is set to 1. 3 not used: 2j2rdie j2 alarm rdi enable: a common control for both the a and b drop bus j2 alarms. a 1 enables a j2 loss of lock or j2 trace mismatch alarm for the active bus to generate either a single bit rdi state or a remote connectivity defect indication (three bit rdi) when control bit rndien is set to 1. 1 uqrdie unequipped alarm rdi enable: a common control for both the a and b drop bus unequipped alarm (a/bnuneq). a 1 enables a unequipped alarm for the active bus to generate either a single bit rdi state or a remote connectivity defect indication (three bit rdi) when control bit rndien is set to 1. 0urdie upstream ais alarm rdi enable: a common control for both the a and b drop bus upstream ais alarm (a/bxuais). a 1 enables an upstream ais alarm for the active bus to generate either a single bit rdi state or a remote server defect indication (three bit rdi) when control bit rndien is set to 1. 039 7-1 not used: 0 dreset a and b drop reset: writing a 1 to this control bit clears all perfor- mance counters to zero (saturating) or the fe/fffe hex values (8/16 bit non-saturating) and alarms, and initializes the internal fifos and state machines for all channels for the a and b drop buses. it does not clear the control bit settings. address bit symbol description
temx8 txc-04218 - 129 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 03a 7 tjust transmit frequency justification control: when set to 0, the fre- quency justification states s1 equal to data and s2 equal to stuff will not be provided. when set to 1, full justification according to the itu stan- dards is enabled. 6pado a/b add bus parity generated on data only: common control bit for both add buses. a 1 causes parity to be calculated over the data byte only. a 0 causes parity to be calculated over the data byte, and the spe and c1j1v1 signals if they enabled as outputs in the drop bus timing mode. please refer to the table provided below for dbpe control bit. 5abpe a/b add bus even parity generated: this bit works in conjunction with the pado control bit to determine the parity calculation in the add direc- tion. drop bus timing mode i (abust = high, abte = low) abpe pado action (for both a and b add buses) 0 0 odd parity generated over add data, spe, and c1j1v1. 0 1 odd parity generated over add data only. 1 0 even parity generated over add data, spe, and c1j1v1. 1 1 even parity generated over add data only. drop bus timing mode ii (abust = high, abte = high) abpe pado action (for both a and b add buses) 0 x odd parity generated over add data only. 1 x even parity generated over add data only. add bus timing mode (abust = low, abte = x) abpe pado action (for both a and b add buses) 0 x odd parity generated over add data only. 1 x even parity generated over add data only. 4tobwz transmit o-bit channel with zeros: a common control for all chan- nels. a 0 enables the microprocessor-written values for the o-bit chan- nel to be transmitted. a 1 forces the o-bit channel to be transmitted as zero for all channels. 3 not used: 2bahze b side add bus high impedance enable: a 0 enables normal opera- tion for the b side add bus. a 1 forces the data output leads (ba(7-0)), and the parity lead (bapar) to a high impedance state. the add indica- tor (badd ) is turned off. in the drop bus timing mode, if the baclk, baspe, and bac1j1v1 signals are enabled as outputs they will be forced to the high impedance state when this bit is set to 1 in addition to the data output leads and parity lead. the add indicator (aadd ) is turned off. 1aahze a side add bus high impedance enable: a 0 enables normal opera- tion for the a side add bus. a 1 forces the data output leads (aa(7-0)), and the parity lead (bapar) to a high impedance state. the add indica- tor (aadd ) is turned off. in the drop bus timing mode, if the aaclk, aaspe, and aac1j1v1 signals are enabled as outputs they will be forced to the high impedance state when this bit is set to 1 in addition to the data output leads and parity lead. the add indicator (badd ) is turned off. address bit symbol description
temx8 txc-04218 - 130 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 03a (cont.) 0 addi add indicator inversion: a 1 causes the a and b add bus output indi- cator signals (aadd and badd ) to be active high instead of active low for all tu/vt added to the a or b buses. 03b 7-3 not used: 2tb2dis transmit disable bip2 tandem connection unequipped: a 1 dis- ables the bip2 (in bits 1 and 2) from being transmitted in an unequipped tandem connection (n2) byte. 1abod add bus output delay: this bit works in conjunction with the abte lead when in drop timing mode. the add bus data, parity, add indicator, and optionally the c1j1v1 and spe (when lead abte is low) are delayed one clock from the drop bus timing when abod is a 0 and two clocks from the drop bus timing when abod is a 1. in add bus timing mode, the add bus data, parity, and add indicator are delayed 1 clock from the add bus timing when abod is a 0 and are delayed 2 clocks from the add bus timing when abod is a 1. 0 thrsby threshold modulation disabled: a 1 disables the threshold modula- tion capability in each of the four modulation circuits. a 0 enables thresh- old modulation capability in each of the four modulation circuits. 03c 7-1 not used: 0treset transmit a and b (add) reset: writing a 1 to this bit clears all perfor- mance counters to zero (saturating) or the fe/fffe hex values (8/16 bit non-saturating) and alarms, and initializes the internal fifos and state machines for all channels for the a and b add buses. it does not clear the control bit settings. address bit symbol description
temx8 txc-04218 - 131 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 mask bits for a and b bus status alarms address bit symbol description 005 7 hint hardware interrupt enable: a 1 enables a hardware interrupt to occur on a bus alarm or polling bit provided the corresponding interrupt mask enable bits (global indication bits mgda, mgdb, mgab, mpcda, mpcdb, and mpcab) in the interrupt structure is set to a 1. a 0 disables the hardware interrupt lead. 6 not used: 5mgda mask bit for global indication for a drop bus alarms: a 1 enables a hardware interrupt for the global indication (gda) for a drop bus alarms when control bit hint is set to 1. a 0 disables the hardware interrupt for the global indication bit gda. 4mgdb mask bit for global indication for b drop bus alarms: a 1 enables a hardware interrupt for the global indication (gdb) for b drop bus alarms when control bit hint is set to 1. a 0 disables the hardware interrupt for the global indication bit gdb. 3mgab mask bit for global indication for a and b add bus alarms: a 1 enables a hardware interrupt for the global indication (gab) for a/b add bus alarms when control bit hint is set to 1. a 0 disables the hardware interrupt for the global indication bit gab. 2mpcda mask bit for global indication for a drop channel alarms: a 1 enables a hardware interrupt for the global indication (pcda) for a drop polling registers (a drop alarms for all channels) when control bit hint is set to 1. a 0 disables the hardware interrupt for the global indication bit pcda. 1mpcdb mask bit for global indication for b drop channel alarms: a 1 enables a hardware interrupt for the global indication (pcdb) for b drop polling registers (b drop alarms for all channels) when control bit hint is set to 1. a 0 disables the hardware interrupt for the global indication bit pcdb. 0mpcab mask bit for global indication for a and b add channel alarms: a 1 enables a hardware interrupt for the global indication (pcab) for a and b add polling registers (a and b add alarms for all channels) when control bit hint is set to 1. a 0 disables the hardware interrupt for the global indication bit pcab.
temx8 txc-04218 - 132 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 007 7 not used: 6mdvcais mask bit vc ais alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a vc ais latched alarm occurs in any channel. a 0 disables a vc ais latched alarm in any channel from setting the corresponding polling bit. 5 mduneq mask bit unequipped alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a unequipped latched alarm occurs in any channel. a 0 disables a unequipped latched alarm in any channel from setting the corresponding polling bit. 4 mdrdic mask bit remote connectivity defect alarm a and b drop all chan- nels: a 1 enables a channel polling register bit for the a and b drop sides to set when a rdi-c latched alarm occurs in any channel. a 0 dis- ables a rdi-c latched alarm in any channel from setting the correspond- ing polling bit. 3 mdrdip mask bit remote payload defect alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a rdi-p latched alarm occurs in any channel. a 0 disables a rdi-p latched alarm in any channel from setting the corresponding poll- ing bit. 2 mdrdis mask bit remote server defect alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a rdi-s or single bit rdi latched alarm occurs in any channel. a 0 disables a rdi-s or single bit rdi latched alarm in any channel from set- ting the corresponding polling bit. 1mdsler mask bit signal label alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a signal label latched alarm occurs in any channel. a 0 disables a signal label latched alarm in any channel from setting the corresponding polling bit. 0mdrfi mask bit remote failure indication alarm a and b drop all chan- nels: a 1 enables a channel polling register bit for the a and b drop sides to set when a remote failure indication latched alarm occurs in any channel. a 0 disables a rfi latched alarm in any channel from setting the corresponding polling bit. address bit symbol description
temx8 txc-04218 - 133 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 008 7-5 not used: 4 mdrffe mask bit desync fifo error alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a desync fifo error latched alarm occurs in any channel. a 0 dis- ables a desync fifo error latched alarm in any channel from setting the corresponding polling bit. 3mdais mask bit ais alarm a and b drop all channels: a 1 enables a chan- nel polling register bit for the a and b drop sides to set when a ais (v1/v2 bytes) latched alarm occurs in any channel. a 0 disables a ais label latched alarm in any channel from setting the corresponding polling bit. 2mdlop mask bit loss of pointer alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a loss of pointer latched alarm occurs in any channel. a 0 disables a loss of pointer latched alarm in any channel from setting the corre- sponding polling bit. 1 mdndf mask bit ndf indication a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a new data flag latched alarm occurs in any channel. a 0 disables a ndf latched alarm in any channel from setting the corresponding polling bit. 0mdsize mask bit size alarm a and b drop all channels: a 1 enables a chan- nel polling register bit for the a and b drop sides to set when a vt/tu size latched alarm occurs in any channel. a 0 disables a vt/tu size latched alarm in any channel from setting the corresponding polling bit. address bit symbol description
temx8 txc-04218 - 134 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 009 7 not used: 6mtais mask bit transmit line ais alarm all channels: a 1 enables a chan- nel polling register bit for the a and b add sides to set when a transmit line ais latched alarm occurs in any channel. a 0 disables a transmit line ais label latched alarm in any channel from setting the corresponding polling bit. 5 mtffe mask bit transmit fifo alarm all channels: a 1 enables a channel polling register bit for the a and b add sides to set when a transmit fifo latched alarm occurs in any channel. a 0 disables a transmit fifo latched alarm in any channel from setting the corresponding polling bit. 4mool mask bit prbs analyzer out of lock alarm: a 1 enables a channel polling register bit for the prbs analyzer to set when an out of lock latched alarm occurs in any channel. a 0 disables a out of lock latched alarm in any channel from setting the corresponding polling bit. 3mtlos mask bit transmit loss of signal alarm all channels: a 1 enables a channel polling register bit for the a and b add sides to set when a trans- mit loss of signal latched alarm occurs in any channel. a 0 disables a transmit los latched alarm in any channel from setting the correspond- ing polling bit. 2mtloc mask bit transmit loss of clock alarm all channels: a 1 enables a channel polling register bit for the a and b add sides to set when a trans- mit loss of clock latched alarm occurs in any channel. a 0 disables a transmit loc latched alarm in any channel from setting the correspond- ing polling bit. 1mdj2tim mask bit j2 trace mismatch alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a j2 trace mismatch latched alarm occurs in any channel. a 0 dis- ables a j2 trace mismatch latched alarm in any channel from setting the corresponding polling bit. 0 mdj2lol mask bit j2 loss of lock alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a j2 loss of lock mismatch latched alarm occurs in any channel. a 0 disables a j2 loss of lock latched alarm in any channel from setting the corresponding polling bit. address bit symbol description
temx8 txc-04218 - 135 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 00a 7 mtclm mask bit tandem connection loss of multiframe alignment alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a tc loss of multiframe latched alarm occurs in any channel. a 0 disables a tc loss of multiframe latched alarm in any channel from setting the corresponding polling bit. 6mtcll mask bit tandem connection loss of lock alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a tc loss of lock latched alarm occurs in any channel. a 0 disables a tc loss of lock latched alarm in any channel from setting the corresponding polling bit. 5 mtctm mask bit tandem connection trace mismatch alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a tc trace mismatch latched alarm occurs in any channel. a 0 disables a tc trace mismatch latched alarm in any chan- nel from setting the corresponding polling bit. 4mtcais mask bit tandem connection ais alarm a and b drop all chan- nels: a 1 enables a channel polling register bit for the a and b drop sides to set when a tc ais latched alarm occurs in any channel. a 0 dis- ables a tc ais latched alarm in any channel from setting the corre- sponding polling bit. 3mtcuq mask bit tandem connection unequi pped alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a tc unequipped latched alarm occurs in any channel. a 0 disables a tc unequipped latched alarm in any channel from setting the corresponding polling bit. 2 mtcrdi mask bit tandem connection remote defect indication alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a tc rdi latched alarm occurs in any channel. a 0 disables a tc rdi latched alarm in any channel from setting the corresponding polling bit. 1mtcodi mask bit tandem connection outgoi ng defect indication alarm a and b drop all channels: a 1 enables a channel polling register bit for the a and b drop sides to set when a tc odi latched alarm occurs in any channel. a 0 disables a tc odi latched alarm in any channel from setting the corresponding polling bit. 0 not used: 03d 7-2 not used: 1mbbloc mask bit b side add bus loss of clock: a 1 enables the global indi- cation gab to set when a add bus loss of clock alarm occurs. a 0 dis- ables the global indication bit gab from setting. 0mabloc mask bit a side add bus loss of clock: a 1 enables the global indi- cation gab to set when a add bus loss of clock alarm occurs. a 0 dis- ables the global indication bit gab from setting. 03f 7-0 mask bits add polling register channel 8-1 mask bits polling registers channels 8-1 add alarms: a 1 in one or more bits enables an a/b side add alarm in the corresponding channel to set the global indication (pcab) bit. a 0 disables the channel corre- sponding to a polling bit from setting the global indication (pcab) bit. bit 7 is the mask bit for channel 8 add side alarms. 040 reserved 041 reserved address bit symbol description
temx8 txc-04218 - 136 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 a and b drop and add bus status alarm registers - descriptions) 042 reserved address bit symbol description 050 7-6 not used: 5gda global indication for a drop bus alarms: this bit position indicates when an a drop bus alarm is detected. this bit sets when any a drop bus latched alarm occurs and the mask bit associated with the alarm is set to 1. an interrupt occurs when the corresponding mask bit mgda (bit 5, 005h) is set to 1, and control bit hint (bit 7, 005h) is set to 1. this bit clears when the latched alarms for the a drop bus are cleared, or the mask bit associated with the alarm in the interrupt hierarchy is set to 0. 4gdb global indication for b drop bus alarms: this bit position indicates when a b drop bus alarm is detected. this bit sets when any b drop bus latched alarm occurs and the mask bit associated with the alarm is set to 1. an interrupt occurs when the corresponding mask bit mgdb (bit 4, 005h) is set to 1, and control bit hint (bit 7, 005h) is set to 1. this bit clears when the latched alarms for the b drop bus are cleared, or the mask bit associated with the alarm in the interrupt hierarchy is set to 0. 3gab global indication for a and b add bus alarms: this bit position indi- cates when an a/b add bus alarm is detected. this bit sets when any latched alarm for the a/b add bus occurs and the mask bit associated with the alarm is set to 1. an interrupt occurs when the corresponding mask bit mgab (bit 3, 005h) is set to 1, and control bit hint (bit 7, 005h) is set to 1. this bit cleared when the latched alarms for the a/b add bus are clears, or the mask bit associated with the alarm in the inter- rupt hierarchy is set to 0. address bit symbol description
temx8 txc-04218 - 137 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 050 (cont.) 2 pcda global indication for a drop channel alarms: this bit position indi- cates when any of the channels has detected an a side drop alarm. this bit sets when any a drop bus latched alarm occurs and the 3 mask bits associated with the alarm are set to 1. an interrupt occurs when the cor- responding mask bit mpcda (bit 2, 005h) is set to 1, and control bit hint (bit 7, 005h) is set to 1. this bit clears when all of the latched alarms for channels 1 through 8 for the a side drop channels are cleared, or one or more latched alarms are asserted, but one or more of the 3 enabling mask bits is set to 0. 1 pcdb global indication for b drop bus channel alarms: this bit position indicates when any of the channels has detected an b side drop alarm. this bit sets when any b drop bus latched alarm occurs and the 3 mask bits associated with the alarm are set to 1. an interrupt occurs when the corresponding mask bit mpcdb (bit 1, 005h) is set to 1, and control bit hint (bit 7, 005h) is set to 1. this bit clears when all of the latched alarms for channels 1 through 8 for the b side drop channels are cleared, or one or more latched alarms are asserted, but one or more of the 3 enabling mask bits is set to 0. 0pcab global indication for a and b add bus channel alarms: this bit position indicates when any of the channels has detected an a/b side add alarm. this bit sets when any latched alarm for the a/b add bus occurs and the 3 mask bits associated with the alarm are set to 1. an interrupt occurs when the corresponding mask bit mpcab (bit 0, 005h) is set to 1, and control bit hint (bit 7, 005h) is set to 1. this bit cleared when all of the latched alarms for channels 1 through 8 for the a/b side add channels are clears, or one or more latched alarms are asserted, but one or more of the 3 enabling mask bits is set to 0. 051 7-2 not used: 1bbloc b add bus loss of clock alarm unlatched alarm indication: a 1 indicates that the b side add bus has detected a loss of clock, when add bus timing is selected. a loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. an alarm occurs when the input add clock is stuck high or low for 56 clock cycles of dsclk. recovery to 0 occurs on the first clock transition. 0abloc a add bus loss of clock alarm unlatched alarm indication: a 1 indicates that the a side add bus has detected a loss of clock, when add bus timing is selected. a loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. an alarm occurs when the input add clock is stuck high or low for 56 clock cycles of dsclk. recovery to 0 occurs on the first clock transition. address bit symbol description
temx8 txc-04218 - 138 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 052 7-2 not used: 1 lbbloc b add bus loss of clock alarm latched alarm indication: this bit position latches when the b side add bus has detected a loss of clock when add bus timing is selected. this bit is set on either a positive transi- tion, negative transition or positive and negative transition. this bit is cleared in a read cycle. 0 labloc a add bus loss of clock alarm latched alarm indication: this bit position latches when the a side add bus has detected a loss of clock when add bus timing is selected. this bit is set on either a positive transi- tion, negative transition or positive and negative transition. this bit is cleared in a read cycle. 053 7-2 not used: 1 pbbloc b add bus loss of clock one second alarm indication: this bit position is set when the b side add bus loss of clock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0 pabloc a add bus loss of clock one second alarm indication: this bit position is set when the a side add bus loss of clock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 054 7-2 not used: 1 fbbloc b add bus loss of clock persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side add bus loss of clock alarm indication is active, but did not become active in the previous one second interval. 0 fabloc a add bus loss of clock persistent one second latched alarm indication: this bit position is set to 1 for the one-second interval, when the a side add bus loss of clock alarm indication is active, but did not become active in the previous one second interval. 055 7-0 polling register add alarms channels 8-1 polling registers, channels 8-1 alarms: bit 7 corresponds to the poll- ing bit for channel 8. a polling bit is set to 1 when one or more a/b add side latched alarms occurs in a channel and the corresponding mask bit is set to 1. this bit is cleared when the add side latched alarms corre- sponding to the channel that is set to 1 are read, or the mask bit associ- ated with the alarm in the interrupt hierarchy is set to 0. 056 reserved 057 reserved 058 reserved address bit symbol description
temx8 txc-04218 - 139 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 mask bits for a drop bus status alarms 059 7-1 not used: 0 resetd reset sequence completed: indication that the hardware reset (reset lead) or software reset (control bit reseth) is completed. it takes approximately 4 microseconds for this bit to set to a 1 after the hardware reset or software reset control bit has been invoked. micropro- cessor access of the temx8 is not valid until this bit is set to 1. this bit goes to zero immediately after the hardware or software reset has been invoked. address bit symbol description 043 7-5 not used: 4ma3uais mask bit for global indication for upstresm ais indication for a drop bus sts-3 sts-1 no.3/stm-1 au-3 c: a 1 enables the global indication (gda) to be set for an upstream ais indication that has been detected in the h1/h2 bytes or in the e1 byte for sts-3 sts-1 no.3/stm-1 au-3 c format for the a side drop bus. a 0 disables the glo- bal indication bit gda for this alarm. 3ma2uais mask bit for global indication for upstream ais indication for a drop bus sts-3 sts-1 no.2/stm-1 au-3 b: a 1 enables the global indication (gda) to be set for an upstream ais indication that has been detected in the h1/h2 bytes or in the e1 byte for sts-3 sts-1 no.2/stm-1 au-3 b format for the a side drop bus. a 0 disables the glo- bal indication bit gda for this alarm. 2ma1uais mask bit for global indication for upstream ais indication for a drop bus sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4: a 1 enables the global indication (gda) to be set for an upstream ais indica- tion that has been detected in the h1/h2 bytes or in the e1 byte for sts-3 sts-1 no.2/stm-1 au-3 a or for the stn-1 vc-4 format for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 1madpar mask bit for global indication for a drop parity alarm: a 1 enables the global indication (gda) to be set for a parity alarm detected for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 0madloc mask bit for global indication for a drop loss of clock alarm: a 1 enables the global indication (gda) to be set for a loss of clock alarm detected for the a side drop bus. a 0 disables the global indication bit gda for this alarm. address bit symbol description
temx8 txc-04218 - 140 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 044 7-6 not used. 5 ma3oom mask bit for global indication for h4 out of multiframe indication for a drop bus sts-3 sts-1 no.3/stm-1 au-3 c: a 1 enables the glo- bal indication (gda) to be set for an h4 out of multiframe indication for sts-3 sts-1 no.3/stm-1 au-3 c format for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 4 ma2oom mask bit for global indication for h4 out of multiframe indication for a drop bus sts-3 sts-1 no.2/stm-1 au-3 b: a 1 enables the glo- bal indication (gda) to be set for an h4 out of multiframe indication for sts-3 sts-1 no.2/stm-1 au-3 b format for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 3 ma1oom mask bit for global indication for h4 out of multiframe indication for a drop bus sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4: a 1 enables the global indication (gda) to be set for an h4 out of multi- frame indication for sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4 format for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 2 ma3lom mask bit for global indication for h4 loss of multiframe indication for a drop bus sts-3 sts-1 no.3/stm-1 au-3 c: a 1 enables the glo- bal indication (gda) to be set for an h4 loss of multiframe indication for sts-3 sts-1 no.3/stm-1 au-3 c format for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 1 ma2lom mask bit for global indication for h4 loss of multiframe indication for a drop bus sts-3 sts-1 no.2/stm-1 au-3 b: a 1 enables the glo- bal indication (gda) to be set for an h4 loss of multiframe indication for sts-3 sts-1 no.2/stm-1 au-3 b format for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 0 ma1lom mask bit for global indication for h4 loss of multiframe indication for a drop bus sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4: a 1 enables the global indication (gda) to be set for an h4 loss of multi- frame indication for sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4 format for the a side drop bus. a 0 disables the global indication bit gda for this alarm. 045 7-0 mask bits a drop polling register channel 8-1 mask bits polling registers channels 8-1 a drop alarms: a 1 in one or more bits enables an a drop side alarm in the corresponding channel to set the global indication (pcda) bit. a 0 disables the channel corre- sponding to a polling bit from setting the global indication (pcda) bit. bit 7 is the mask bit for channel 8 a drop side alarms. 046 reserved 047 reserved 048 reserved address bit symbol description
temx8 txc-04218 - 141 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 a side drop bus - status register descriptions address bit symbol description 060 7-5 not used: 4a3uais a side drop bus upstream ais (unlatched) alarm indication - sts-3 sts-1 no. 3/au-3 c: a 1 indicates that ais has been detected on the a side drop bus in the h1/h2 bytes or in the e13 byte for the sts-3 sts-1 no.3/stm-1 au-3 c format. control bits se1ais and heaise (bits 1 and 0, 01dh) determine whether the h1/h2 bytes or the e13 byte is monitored for ais detection. this indication is disabled for the stm-1 vc-4 format. 3a2uais a side drop bus upstream ais (unlatched) alarm indication - sts-3 sts-1 no. 2/au-3 b: a 1 indicates that ais has been detected on the a side drop bus in the h1/h2 bytes or in the e12 byte for the sts-3 sts-1 no.2/stm-1 au-3 b format. control bits se1ais and heaise (bits 1 and 0, 01dh) determine whether the h1/h2 bytes or the e12 byte is monitored for ais detection. this indication is disabled for the stm-1 vc-4 format. 2a1uais a side drop bus upstream ais (unlatched) alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc4: a 1 indicates that ais has been detected on the a side drop bus in the h1/h2 bytes or in the e11 byte for the sts-3 sts-1 no.1/stm-1 au-3 a format or for the stm-1 vc-4 format. control bits se1ais and heaise (bits 1 and 0, 01dh) determine whether the h1/h2 bytes or the e11 byte is monitored for ais detection. 1adpar a side drop bus parity (unlatched) alarm indication: a 1 indicates that an even or odd parity error has been detected in the a side drop bus signals. other than an alarm indication, no action is taken. parity is mon- itored for each drop bus clock cycle. 0adloc a side drop bus loss of clock unlatched alarm indication: a 1 indicates that the a side drop bus has detected a loss of clock. an alarm occurs when the input drop clock is stuck high or low for 56 clock cycles (dsclk clock). recovery occurs on the first clock transition.
temx8 txc-04218 - 142 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 061 7-6 not used: 5 a3hoom a side drop bus h4 byte out of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 3/au-3 c: enabled when control bit dv1sel is a 0. an out of multiframe alarm for sts-3 sts-1 no. 3/au-3 c is declared once an error is detected in the bit 7 and 8 sequence in the h4 byte. recovery occurs when an error-free h4 sequence (00, 01, 10, 11) is found in four consecutive frames. 4 a2hoom a side drop bus h4 byte out of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 2/au-3 b: enabled when control bit dv1sel is a 0. an out of multiframe alarm for sts-3 sts-1 no. 2/au-3 b is declared once an error is detected in the bit 7 and 8 sequence in the h4 byte. recovery occurs when an error-free h4 sequence (00, 01, 10, 11) is found in four consecutive frames. 3 a1hoom a side drop bus h4 byte out of multiframe alignment (unlatched) alarm - sts-3 sts-1/au-3 a, stm-1 vc-4: enabled when control bit dv1sel is a 0. an out of multiframe alarm for sts-3 sts-1 no.1/au-3 or the stm-1 vc-4 is declared once an error is detected in the bit 7 and 8 sequence in the h4 byte. recovery occurs when an error-free h4 sequence (00, 01, 10, 11) is found in four consecutive frames. 2 a3hlom a side drop bus h4 byte loss of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 3/au-3 c: once in the out of multiframe state, if recovery does not occur within 1 ms, a loss of multiframe alarm is declared. recovery will occur when the multiframe is recovered. the loss of multiframe alarm forces a vt/tu loss of pointer alarm (anlop) for all channels which have a vt/tu selected for sts-3 sts-1 no. 3/au-3 c. 1 a2hlom a side drop bus h4 byte loss of multiframe alignment (unlatched) alarm - sts-3 sts-1no. 2/au-3 b: once in the out of multiframe state, if recovery does not occur within 1 ms, a loss of multiframe alarm is declared. recovery will occur when the multiframe is recovered. the loss of multiframe alarm forces a vt/tu loss of pointer alarm (anlop) for all channels which have a vt/tu selected for sts-3 sts-1no. 2/au-3 b. 0 a1hlom a side drop bus h4 byte loss of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: once in the out of multiframe state, if recovery does not occur within 1 ms, a loss of multi- frame alarm is declared. recovery will occur when the multiframe is recovered. the loss of multiframe alarm forces a vt/tu loss of pointer alarm (anlop) for all channels which have a vt/tu selected for sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4. address bit symbol description
temx8 txc-04218 - 143 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 062 7-5 not used: 4la3uais a side drop bus upstream ais latched alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position latches for the a side received upstream ais alarm indication for the sts-3 sts-1 no. 3/au-3 c for- mat. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3la2uais a side drop bus upstream ais latched alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position latches for the a side received upstream ais alarm indication for the sts-3 sts-1 no. 2/au-3 b for- mat. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2la1uais a side drop bus upstream ais latched alarm indication - sts-3 sts-1 no. 1/au-3 a/vc4: this bit position latches for the a side received upstream ais alarm indication for the sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4 format. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 1ladpar a side drop bus parity latched alarm indication: this bit position latches for the a side parity error. this bit is set on either a positive tran- sition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0ladloc a side drop bus loss of clock latched alarm indication: this bit position latches for the a side loss of clock alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 144 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 063 7-6 not used: 5 la3hoom a side drop bus h4 byte out of multiframe alignment latched alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position latches for the a side sts-3 sts-1 no. 3/au-3 c h4 byte out of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 4 la2hoom a side drop bus h4 byte out of multiframe alignment latched alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position latches for the a side sts-3 sts-1 no.2/au-3 b h4 byte out of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3 la1hoom a side drop bus h4 byte out of multiframe alignment latched alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position latches for the a side sts-3 sts-1 no.1/au-3 a, or stm-1 vc-4 h4 byte out of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2la3hlom a side drop bus h4 byte loss of multiframe alignment latched alarm indication - sts-3 sts-1 no. 2/au-3 c: this bit position latches for the a side sts-3 sts-1 no. 3/au-3 c h4 byte loss of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 1la2hlom a side drop bus h4 byte loss of multiframe alignment latched alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position latches for the a side sts-3 sts-1 no. 2/au-3 b h4 byte loss of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0la1hlom a side drop bus h4 byte loss of multiframe alignment latched alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position latches for the a side sts-3 sts-1 no. 1/au-3 a, or stm-1 vc-4 h4 byte loss of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 145 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 064 7-5 not used: 4pa3uais a side drop bus upstream ais one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set when the a side received upstream ais alarm indication - sts-3 sts-1 no. 3/au-3 c has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3pa2uais a side drop bus upstream ais one second alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position is set when the a side received upstream ais alarm indication - sts-3 sts-1 no. 2/au-3 b has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2pa1uais a side drop bus upstream ais one second alarm indication - sts-1 no. 1/au-3 a and stm-1 vc-4: this bit position is set when the a side received upstream ais alarm indication - sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4 has changed state in the last one second inter- val or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1padpar a side drop bus parity one second alarm indication: this bit posi- tion is set when the a side parity error alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0padloc a side drop bus loss of clock one second alarm indication: this bit position is set when the a side loss of clock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 146 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 065 7-6 not used: 5 pa3hoom a side drop bus h4 byte out of multiframe alignment one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set when the a side sts-3 sts-1 no. 3/au-3 c h4 byte out of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 4 pa2hoom a side drop bus h4 byte out of multiframe alignment one second alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position is set when the a side sts-3 sts-1 no. 2/au-3 b h4 byte out of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3 pa1hoom a side drop bus h4 byte out of multiframe alignment one second alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set when the a side sts-3 sts-1 no. 1/au-3 a or the stm-1 vc-4 h4 byte out of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2pa3hlom a side drop bus h4 byte loss of multiframe alignment one sec- ond alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set when the a side sts-3 sts-1 no. 3/au-3 c h4 byte loss of multi- frame alignment alarm indication has changed state in the last one sec- ond interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1pa2hlom a side drop bus h4 byte loss of multiframe alignment one sec- ond alarm indication - sts-1 no. 2/au-3 b: this bit position is set when the a side sts-3 /sts-1 no. 2/au-3 b h4 byte loss of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0pa1hlom a side drop bus h4 byte loss of multiframe alignment one sec- ond alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set when the a side sts-3 sts-1 no.1/au-3 a or the stm-1 vc-4 h4 byte loss of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 147 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 066 7-5 not used: 4fa3uais a side received upstream ais persistent one second alarm indi- cation - sts-3 sts-1 no. 3/au-3 c: this bit position is set to 1 for the one-second interval, when the a side received upstream ais alarm indi- cation - sts-3 sts-1 no. 3/au-3 c is active, but did not become active in the previous one second interval. 3fa2uais a side received upstream ais persistent one second alarm indi- cation - sts-3 sts-1 no. 2/au-3 b: this bit position is set to 1 for the one-second interval, when the a side received upstream ais alarm indi- cation - sts-3 sts-1 no. 2/au-3 b is active, but did not become active in the previous one second interval. 2fa1uais a side received upstream ais persistent one second alarm indi- cation - sts-3 sts-1 no. 1/au-3 a and stm-1 vc-4: this bit position is set to 1 for the one-second interval, when the a side received upstream ais alarm indication - sts-3 sts-1 no. 1/au-3 a or sm-1 vc-4 is active, but did not become active in the previous one second interval. 1fadpar a side drop bus parity persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the a side parity error alarm indication is active, but did not become active in the previous one second interval. 0fadloc a side drop bus loss of clock persistent one second alarm indi- cation: this bit position is set to 1 for the one-second interval, when the a side loss of clock alarm indication is active, but did not become active in the previous one second interval. address bit symbol description
temx8 txc-04218 - 148 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 067 7-6 not used: 5 fa3hoom a side drop bus h4 byte out of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set to 1 for the one-second interval, when the a side sts-3 sts-1 no. 3/au-3 c h4 byte out of multiframe alarm indication is active, but did not become active in the previous one second interval. 4 fa2hoom a side drop bus h4 byte out of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 2/3au-3 b: this bit position is set to 1 for the one-second interval, when the a side sts-3 sts-1 no. 2/au-3 b h4 byte out of multiframe alarm indication is active, but did not become active in the previous one second interval. 3 fa1hoom a side drop bus h4 byte out of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set to 1 for the one-second interval, when the a side sts-3 sts-1 no. 1/au-3 a, or the stm-1 vc-4 h4 byte out of multiframe alarm indication is active, but did not become active in the previous one second interval. 2fa3hlom a side drop bus h4 byte loss of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set to 1 for the one-second interval, when the a side sts-3 sts-1 no. 3/au-3 c h4 byte loss of multiframe alarm indication is active, but did not become active in the previous one second interval. 1fa2hlom a side drop bus h4 byte loss of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position is set to 1 for the one-second interval, when the a side sts-3 sts-1 no. 2/au-3 b h4 byte loss of multiframe alarm indication is active, but did not become active in the previous one second interval. 0fa1hlom a side drop bus h4 byte loss of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set to 1 for the one-second interval, when the a side sts-3 sts-1 no. 1/au-3 a, or the stm-1 vc-4 h4 byte loss of multiframe alarm indication is active, but did not become active in the previous one second interval. 068 7-0 a side drop bus h1 byte a side drop bus h1 pointer byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped h1 pointer byte in the a drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register cor- respond to bits 1-8 of the h1 byte. 069 7-0 a side drop bus h1 byte a side drop bus h1 pointer byte for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped h1 pointer byte in the a drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h1 byte. address bit symbol description
temx8 txc-04218 - 149 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 06a 7-0 a side drop bus h1 byte a side drop bus h1 pointer byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped h1 pointer byte in the a drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h1 byte. 06b 7-0 a side drop bus h2 byte a side drop bus h2 pointer byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped h2 pointer byte in the a drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register cor- respond to bits 1-8 of the h2 byte. 06c 7-0 a side drop bus h2 byte a side drop bus h2 pointer byte for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped h2 pointer byte in the a drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h2 byte. 06d 7-0 a side drop bus h2 byte a side drop bus h2 pointer byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped h2 pointer byte in the a drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h2 byte. 06e 7-0 a side drop bus h4 byte a side drop bus h4 path overhead byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped h4 path overhead byte in the a drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h4 byte. 06f 7-0 a side drop bus h4 byte a side drop bus h4 path overhead byte for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped h4 path overhead byte in the a drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h4 byte. 070 7-0 a side drop bus h4 byte a side drop bus h4 path overhead byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped h4 path overhead byte in the a drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h4 byte. 071 7-0 a side drop bus e1 byte a side drop bus e1 overhead byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped e1 overhead byte in the a drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register cor- respond to bits 1-8 of the e1 byte. 072 7-0 a side drop bus e1 byte a side drop bus e12 overhead by te for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped e1 overhead byte in the a drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the e1 byte. address bit symbol description
temx8 txc-04218 - 150 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 mask bits for b drop bus status alarms 073 7-0 a side drop bus e1 byte a side drop bus e1 overhead byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped e1 overhead byte in the a drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the e1 byte. 074 7-0 a side drop bus polling bits channels 8-1 a side drop polling registers, channels 8-1: bit 7 corresponds to the polling bit for channel 8. a polling bit is set to 1 when one or more a side drop alarms are detected in a channel and the corresponding mask bit is set to 1. this bit is cleared when the a side latched alarms correspond- ing to the channel that is set to 1 are read, or the mask bit associated with the alarm in the interrupt hierarchy is set to 0. 075 reserved 076 reserved 077 reserved address bit symbol description 049 7-5 not used: 4mb3uais mask bit for global indication for upstream ais indication for b drop bus sts-3 sts-1 no.3/stm-1 au-3 c: a 1 enables the global indication (gdb) to be set for an upstream ais indication that has been detected in the h1/h2 bytes or in the e1 byte for sts-3 sts-1 no.3/stm-1 au-3 c format for the b side drop bus. a 0 disables the glo- bal indication bit gdb for this alarm. 3mb2uais mask bit for global indication for upstream ais indication for b drop bus sts-3 sts-1 no.2/stm-1 au-3 b: a 1 enables the global indication (gdb) to be set for an upstream ais indication that has been detected in the h1/h2 bytes or in the e1 byte for sts-3 sts-1 no.2/stm-1 au-3 b format for the b side drop bus. a 0 disables the glo- bal indication bit gdb for this alarm. 2mb1uais mask bit for global indication for upstream ais indication for b drop bus sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4: a 1 enables the global indication (gdb) to be set for an upstream ais indica- tion that has been detected in the h1/h2 bytes or in the e1 byte for sts-3 sts-1 no.2/stm-1 au-3 a or for the stn-1 vc-4 format for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 1mbdpar mask bit for global indication for b drop parity alarm: a 1 enables the global indication (gdb) to be set for a parity alarm detected for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 0mbdloc mask bit for global indication for b drop loss of clock alarm: a 1 enables the global indication (gdb) to be set for a loss of clock alarm detected for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. address bit symbol description
temx8 txc-04218 - 151 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 04a 7-6 not used: 5 mb3oom mask bit for global indication for h4 out of multiframe indication for b drop bus sts-3 sts-1 no.3/stm-1 au-3 c: a 1 enables the glo- bal indication (gdb) to be set for an h4 out of multiframe indication for sts-3 sts-1 no.3/stm-1 au-3 c format for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 4 mb2oom mask bit for global indication for h4 out of multiframe indication for b drop bus sts-3 sts-1 no.2/stm-1 au-3 b: a 1 enables the glo- bal indication (gdb) to be set for an h4 out of multiframe indication for sts-3 sts-1 no.2/stm-1 au-3 b format for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 3 mb1oom mask bit for global indication for h4 out of multiframe indication for b drop bus sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4: a 1 enables the global indication (gdb) to be set for an h4 out of multi- frame indication for sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4 format for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 2mb3lom mask bit for global indication for h4 loss of multiframe indication for b drop bus sts-3 sts-1 no.3/stm-1 au-3 c: a 1 enables the glo- bal indication (gdb) to be set for an h4 loss of multiframe indication for sts-3 sts-1 no.3/stm-1 au-3 c format for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 1mb2lom mask bit for global indication for h4 loss of multiframe indication for b drop bus sts-3 sts-1 no.2/stm-1 au-3 b: a 1 enables the glo- bal indication (gdb) to be set for an h4 loss of multiframe indication for sts-3 sts-1 no.2/stm-1 au-3 b format for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 0mb1lom mask bit for global indication for h4 loss of multiframe indication for b drop bus sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4: a 1 enables the global indication (gdb) to be set for an h4 loss of multi- frame indication for sts-3 sts-1 no.1/stm-1 au-3 a and stm-1 vc-4 format for the b side drop bus. a 0 disables the global indication bit gdb for this alarm. 04b 7-0 mask bits b drop polling register channel 8-1 mask bits polling registers channels 8-1 b drop alarms: a 1 in one or more bits enables a b side drop alarm in the corresponding channel to set the global indication (pcdb) bit. a 0 disables the channel corre- sponding to a polling bit from setting the global indication (pcdb) bit. bit 7 is the mask bit for channel 8 b drop side alarms. 04c reserved 04d reserved 04e reserved address bit symbol description
temx8 txc-04218 - 152 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 b side drop bus - status register descriptions address bit symbol description 080 7-5 not used: 4b3uais b side drop bus upstream ais (unlatched) alarm indication - sts-3 sts-1 no. 3/au-3 c: a 1 indicates that ais has been detected on the b side drop bus in the h1/h2 bytes or in the e13 byte for the sts-3 sts-1 no.3/stm-1 au-3 c format. control bits se1ais and heaise (bits 1 and 0, 01dh) determine whether the h1/h2 bytes or the e13 byte is monitored for ais detection. this indication is disabled for the stm-1 vc-4 format. 3b2uais b side drop bus upstream ais (unlatched) alarm indication - sts-3 sts-1 no. 2/au-3 b: a 1 indicates that ais has been detected on the b side drop bus in the h1/h2 bytes or in the e12 byte for the sts-3 sts-1 no.2/stm-1 au-3 b format. control bits se1ais and heaise (bits 1 and 0, 01dh) determine whether the h1/h2 bytes or the e12 byte is monitored for ais detection. this indication is disabled for the stm-1 vc-4 format. 2b1uais b side drop bus upstream ais (unlatched) alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc4: a 1 indicates that ais has been detected on the b side drop bus in the h1/h2 bytes or in the e11 byte for the sts-3 sts-1 no.1/stm-1 au-3 a format or for the stm-1 vc-4 format. control bits se1ais and heaise (bits 1 and 0, 01dh) determine whether the h1/h2 bytes or the e11 byte is monitored for ais detection. 1bdpar b side drop bus parity (unlatched) alarm indication: a 1 indicates that an even or odd parity error has been detected in the b side drop bus signals. other than an alarm indication, no action is taken. parity is mon- itored for each drop bus clock cycle. 0bdloc b side drop bus loss of clock (unlatched) alarm indication: a 1 indicates that the b side drop bus has detected a loss of clock. an alarm occurs when the input drop clock is stuck high or low for 56 clock cycles (dsclk clock). recovery occurs on the first clock transition.
temx8 txc-04218 - 153 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 081 7-6 not used: 5 b3hoom b side drop bus h4 byte out of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 3/au-3 c: enabled when control bit dv1sel is a 0. an out of multiframe alarm for sts-3 sts-1 no. 3/au-3 c is declared once an error is detected in the bit 7 and 8 sequence in the h4 byte. recovery occurs when an error-free h4 sequence (00, 01, 10, 11) is found in four consecutive frames. 4 b2hoom b side drop bus h4 byte out of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 2/au-3 b: enabled when control bit dv1sel is a 0. an out of multiframe alarm for sts-3 sts-1 no. 2/au-3 b is declared once an error is detected in the bit 7 and 8 sequence in the h4 byte. recovery occurs when an error-free h4 sequence (00, 01, 10, 11) is found in four consecutive frames. 3 b1hoom b side drop bus h4 byte out of multiframe alignment (unlatched) alarm - sts-3 sts-1/au-3 a, stm-1 vc-4: enabled when control bit dv1sel is a 0. an out of multiframe alarm for sts-3 sts-1 no.1/au-3 or the stm-1 vc-4 is declared once an error is detected in the bit 7 and 8 sequence in the h4 byte. recovery occurs when an error-free h4 sequence (00, 01, 10, 11) is found in four consecutive frames. 2 b3hlom b side drop bus h4 byte loss of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 3/au-3 c: once in the out of multiframe state, if recovery does not occur within 1 ms, a loss of multiframe alarm is declared. recovery will occur when the multiframe is recovered. the loss of multiframe alarm forces a vt/tu loss of pointer alarm (bnlop) for all channels which have a vt/tu selected for sts-3 sts-1 no. 3/au-3 c. 1 b2hlom b side drop bus h4 byte loss of multiframe alignment (unlatched) alarm - sts-3 sts-1no. 2/au-3 b: once in the out of multiframe state, if recovery does not occur within 1 ms, a loss of multiframe alarm is declared. recovery will occur when the multiframe is recovered. the loss of multiframe alarm forces a vt/tu loss of pointer alarm (bnlop) for all channels which have a vt/tu selected for sts-3 sts-1no. 2/au-3 b. 0 b1hlom b side drop bus h4 byte loss of multiframe alignment (unlatched) alarm - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: once in the out of multiframe state, if recovery does not occur within 1 ms, a loss of multi- frame alarm is declared. recovery will occur when the multiframe is recovered. the loss of multiframe alarm forces a vt/tu loss of pointer alarm (bnlop) for all channels which have a vt/tu selected for sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4. address bit symbol description
temx8 txc-04218 - 154 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 082 7-5 not used: 4lb3uais b side drop bus upstream ais latched alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position latches for the b side received upstream ais alarm indication for the sts-3 sts-1 no. 3/au-3 c for- mat. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3lb2uais b side drop bus upstream ais latched alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position latches for the b side received upstream ais alarm indication for the sts-3 sts-1 no. 2/au-3 b for- mat. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2lb1uais b side drop bus upstream ais latched alarm indication - sts-3 sts-1 no. 1/au-3 a/vc4: this bit position latches for the b side received upstream ais alarm indication for the sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4 format. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 1lbdpar b side drop bus parity latched alarm indication: this bit position latches for the b side parity error. this bit is set on either a positive tran- sition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0lbdloc b side drop bus loss of clock latched alarm indication: this bit position latches for the b side loss of clock alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 155 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 083 7-6 not used: 5 lb3hoom b drop bus h4 byte out of multiframe alignment latched alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position latches for the b side sts-3 sts-1 no. 3/au-3 c h4 byte out of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 4 lb2hoom b drop bus h4 byte out of multiframe alignment latched alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position latches for the b side sts-3 sts-1 no.2/au-3 b h4 byte out of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3 lb1hoom b drop bus h4 byte out of multiframe alignment latched alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position latches for the b side sts-3 sts-1 no.1/au-3 a, or stm-1 vc-4 h4 byte out of multiframe alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2lb3hlom b drop bus h4 byte loss of multiframe alignment latched alarm indication - sts-3 sts-1 no. 2/au-3 c: this bit position latches for the b side sts-3 sts-1 no. 3/au-3 c h4 byte loss of multiframe alarm. this bit is set on either a positive transition, negative transition or posi- tive and negative alarm transition. this bit is cleared on a read cycle. 1lb2hlom b drop bus h4 byte loss of multiframe alignment latched alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position latches for the b side sts-3 sts-1 no. 2/au-3 b h4 byte loss of multiframe alarm. this bit is set on either a positive transition, negative transition or posi- tive and negative alarm transition. this bit is cleared on a read cycle. 0lb1hlom b drop bus h4 byte loss of multiframe alignment latched alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position latches for the b side sts-3 sts-1 no. 1/au-3 a, or stm-1 vc-4 h4 byte loss of multiframe alarm. this bit is set on either a positive transi- tion, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 156 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 084 7-5 not used: 4pb3uais b side drop bus upstream ais one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set when the b side received upstream ais alarm indication - sts-3 sts-1 no. 3/au-3 c has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3pb2uais b side drop bus upstream ais one second alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position is set when the b side received upstream ais alarm indication - sts-3 sts-1 no. 2/au-3 b has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2pb1uais b side drop bus upstream ais one second alarm indication - sts-1 no. 1/au-3 a and stm-1 vc-4: this bit position is set when the b side received upstream ais alarm indication - sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4 has changed state in the last one second inter- val or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1pbdpar b side drop bus parity one second alarm indication: this bit posi- tion is set when the b side parity error alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0pbdloc b side drop bus loss of clock one second alarm indication: this bit position is set when the b side loss of clock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 157 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 085 7-6 not used: 5 pb3hoom b side drop bus h4 byte out of multiframe alignment one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set when the b side sts-3 sts-1 no. 3/au-3 c h4 byte out of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 4 pb2hoom b side drop bus h4 byte out of multiframe alignment one second alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position is set when the b side sts-3 sts-1 no. 2/au-3 b h4 byte out of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3 pb1hoom b side drop bus h4 byte out of multiframe alignment one second alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set when the b side sts-3 sts-1 no. 1/au-3 a or the stm-1 vc-4 h4 byte out of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2pb3hlom b side drop bus h4 byte loss of multiframe alignment one sec- ond alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set when the b side sts-3 sts-1 no. 3/au-3 c h4 byte loss of multi- frame alignment alarm indication has changed state in the last one sec- ond interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1pb2hlom b side drop bus h4 byte loss of multiframe alignment one sec- ond alarm indication - sts-1 no. 2/au-3 b: this bit position is set when the b side sts-3 /sts-1 no. 2/au-3 b h4 byte loss of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0pb1hlom b side drop bus h4 byte loss of multiframe alignment one sec- ond alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set when the b side sts-3 sts-1 no.1/au-3 a or the stm-1 vc-4 h4 byte loss of multiframe alignment alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 158 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 086 7-5 not used: 4fb3uais b side drop bus upstream ais persistent one second alarm indi- cation - sts-3 sts-1 no. 3/au-3 c: this bit position is set to 1 for the one-second interval, when the b side received upstream ais alarm indi- cation - sts-3 sts-1 no. 3/au-3 c is active, but did not become active in the previous one second interval. 3fb2uais b side drop bus upstream ais persistent one second alarm indi- cation - sts-3 sts-1 no. 2/au-3 b: this bit position is set to 1 for the one-second interval, when the b side received upstream ais alarm indi- cation - sts-3 sts-1 no. 2/au-3 b is active, but did not become active in the previous one second interval. 2fb1uais b side drop bus upstream ais persistent one second alarm indi- cation - sts-3 sts-1 no. 1/au-3 a and stm-1 vc-4: this bit position is set to 1 for the one-second interval, when the b side received upstream ais alarm indication - sts-3 sts-1 no. 1/au-3 a or sm-1 vc-4 is active, but did not become active in the previous one second interval. 1fbdpar b side drop bus parity persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side parity error alarm indication is active, but did not become active in the previous one second interval. 0fbdloc b side drop bus loss of clock persistent one second alarm indi- cation: this bit position is set to 1 for the one-second interval, when the b side loss of clock alarm indication is active, but did not become active in the previous one second interval. address bit symbol description
temx8 txc-04218 - 159 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 087 7-6 not used: 5fb3hoom b side drop bus h4 byte out of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set to 1 for the one-second interval, when the b side sts-3 sts-1 no. 3/au-3 c h4 byte out of multiframe alarm indication is active, but did not become active in the previous one second interval. 4fb2hoom b side drop bus h4 byte out of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 2/3au-3 b: this bit position is set to 1 for the one-second interval, when the b side sts-3 sts-1 no. 2/au-3 b h4 byte out of multiframe alarm indication is active, but did not become active in the previous one second interval. 3fb1hoom b side drop bus h4 byte out of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set to 1 for the one-second interval, when the b side sts-3 sts-1 no. 1/au-3 a, or the stm-1 vc-4 h4 byte out of multiframe alarm indication is active, but did not become active in the previous one second interval. 2fb3hlom b side drop bus h4 byte loss of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 3/au-3 c: this bit position is set to 1 for the one-second interval, when the b side sts-3 sts-1 no. 3/au-3 c h4 byte loss of multiframe alarm indication is active, but did not become active in the previous one second interval. 1fb2hlom b side drop bus h4 byte loss of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 2/au-3 b: this bit position is set to 1 for the one-second interval, when the b side sts-3 sts-1 no. 2/au-3 b h4 byte loss of multiframe alarm indication is active, but did not become active in the previous one second interval. 0fb1hlom b side drop bus h4 byte loss of multiframe alignment persistent one second alarm indication - sts-3 sts-1 no. 1/au-3 a, stm-1 vc-4: this bit position is set to 1 for the one-second interval, when the b side sts-3 sts-1 no. 1/au-3 a, or the stm-1 vc-4 h4 byte loss of multiframe alarm indication is active, but did not become active in the previous one second interval. 088 7-0 b side drop bus h1 byte b side drop bus h1 pointer byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped h1 pointer byte in the b drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register cor- respond to bits 1-8 of the h1 byte. 089 7-0 b side drop bus h1 byte b side drop bus h1 pointer byte for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped h1 pointer byte in the b drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h1 byte. address bit symbol description
temx8 txc-04218 - 160 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 08a 7-0 b side drop bus h1 byte b side drop bus h1 pointer byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped h1 pointer byte in the b drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h1 byte. 08b 7-0 b side drop bus h2 byte b side drop bus h2 pointer byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped h21 pointer byte in the b drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register cor- respond to bits 1-8 of the h2 byte. 08c 7-0 b side drop bus h2 byte b side drop bus h2 pointer byte for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped h2 pointer byte in the b drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h2 byte. 08d 7-0 b side drop bus h2 byte b side drop bus h2 pointer byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped h2 pointer byte in the b drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h2 byte. 08e 7-0 b side drop bus h4 byte b side drop bus h4 path overhead byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped h4 path overhead byte in the b drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h4 byte. 08f 7-0 b side drop bus h4 byte b side drop bus h4 path overhead byte for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped h4 path overhead byte in the b drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h4 byte. 090 7-0 b side drop bus h4 byte b side drop bus h4 path overhead byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped h4 path overhead byte in the b drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the h4 byte. 091 7-0 b side drop bus e1 byte b side drop bus e1 overhead byte for sts-3 sts-1 no. 1/au-3 a or stm-1 vc-4: the value in this location is dropped e1 overhead byte in the b drop bus sts-3 sts-1 no. 1/au-3 a or vc-4 format. this register location is updated every 125 microseconds. bits 7-0 of the register cor- respond to bits 1-8 of the e1 byte. 092 7-0 b side drop bus e1 byte b side drop bus e1 overhead byte for sts-3 sts-1 no. 2/au-3 b: the value in this location is dropped e1 overhead byte in the b drop bus sts-3 sts-1 no. 2/au-3 b format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the e1 byte. address bit symbol description
temx8 txc-04218 - 161 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a and b side drop and add bus control register descriptions (n = 1 to 8) 093 7-0 b side drop bus e1 byte b side drop bus e1 overhead byte for sts-3 sts-1 no. 3/au-3 c: the value in this location is dropped e1 overhead byte in the b drop bus sts-3 sts-1 no. 3/au-3 c format. this register location is updated every 125 microseconds. bits 7-0 of the register correspond to bits 1-8 of the e1 byte. 094 7-0 b side drop bus polling bits channels 8-1 b side drop polling registers, channels 8-1: bit 7 corresponds to the polling bit for channel 8. a polling bit is set to 1 when one or more b side drop alarms are detected in a channel and the corresponding mask bit is set to 1. this bit is cleared when the b side latched alarms correspond- ing to the channel that is set to 1 are read, or the mask bit associated with the alarm in the interrupt hierarchy is set to 0. 095 reserved 096 reserved 097 reserved address bit symbol description x+000 7-6 not used: 5 rnnrzp receive data invert enable for nrz data: a 1 inverts the receive nrz data stream when the nrz interface is selected. a 0 enables normal oper- ation. 4 not used: 3rnclki receive clock invert enable: valid for all interfaces. when this control bit is set to 1, data and any other line signals, shall be clocked out on pos- itive transitions of the clock. when set to 0, the line signals are clocked out on negative transitions of the clock. 2 rnb8zs receive b8zs line code enable. when the receive line is configured for rail operation, a 1 selects the b8zs line code for ds1 line interfaces. a 0 selects the ami code. for e1 interfaces this bit must be set to 1 for the hdb3 line code. when set to 0, the ami code is selected. 1 not used: 0 rnlais receive ais sent on line loopback: this bit works in conjunction with control bit lnlbk according to the following table: rnlais lnlbk receive line interface x 0 normal operation. 0 1 line loopback enabled. receive data is provided. 1 1 line loopback enabled. receive ais is sent. x= don?t care x+001 7-0 reserved address bit symbol description
temx8 txc-04218 - 162 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+002 7 6 tnlint1 tnlint0 transmit line interface selection: the transmit line interface is selected according to the following table: tnlint1 tnlint0 line interface selected 0 0 not used. 0 1 nrz interface. the negative rail lead may be used to input an external loss of signal indication or external coding violations. 1 0 rail interface. b8zs or ami line code for the ds1 line rate. hdb3 or ami line code for the e1 line rate. 1 1 vt/tu interface. the tnsel1 and tnsel0 control bits cannot be set to 11 (dual unidirectional ring mode). 5tnnrzp transmit data invert enable for nrz data: a 1 inverts the transmit nrz data stream when the nrz interface is selected. a 0 enables normal oper- ation. 4 tne1sl transmit line rate selection: a 1 selects the e1 line rate for channel n. a 0 selects the ds1 line rate. 3tnclki transmit clock invert enable: valid for all interfaces. when this control bit is set to 0, data and any other line signals, shall be clocked in on nega- tive transitions of the clock. when set to 1, the line signals are clocked in on positive transitions of the clock. 2tnb8zs transmit b8zs line code enable: when the transmit line is configured for rail operation, a 1 selects the b8zs line code for t1 line interfaces. a 0 selects the ami code. for e1 interfaces this bit must be set to 1 for the hdb3 line code. when set to 0, the ami code is selected. 1tnsais sent transmit line ais: a 1 forces either a ds1 or e1 line ais signal to be transmitted for the vt/tu selected in the add direction independent of the add side alarms. 0tnaise transmit line ais enable: enables a ds1 or e1 line ais to be sent for the following conditions: - when control bit tnaise is a 1 - transmit loss of clock alarm (tnloc) - transmit loss of signal alarm (tnlos) when the rail interface is selected - external loss of signal alarm (tnlos) when nrz interface is selected and control bit exnlos is a 1 - control bit tnsais is a 1 - when control bit tnaise is a 0 - control bit tnsais is a 1 note: when control bit tnaise is a 0 and the transmit loss of clock (tnloc) alarm occurs, transmit line ais may be generated regardless of the state of control bit tnsais address bit symbol description
temx8 txc-04218 - 163 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+003 7-2 not used: 1exnlos transmit external loss of signal enable: enabled only when the trans- mit nrz interface is selected. a 1 configures the negative rail interface lead for an external loss of signal indication, a 0 configures the negative rail interface lead for external coding violations. the coding violation active true state is positive. 0 exnlosp transmit external loss of signal sense selection: enabled only when control bit exnlos above is a 1. a 1 configures the loss of signal active true state to be positive. a 0 configures the loss of signal active true state to be negative. x+004 7-6 not used: 5tnptg pbrs generator enable: a 1 enables the prbs generator for channel n. the prbs pattern is selected by control bit tnprn. 4tnanz prbs analyzer enable: a 1 enables the prbs analyzer for channel n. the prbs pattern is selected by control bit tnprn. 3 not used: 2tnprn prbs pattern selection: the test generator and analyzer prbs pattern is selected according to the following table. tnprn p rbs pattern 02 15 -1 pattern. 12 20 -1 qrs pattern. 1lnlbk line loopback: a 1 enables a ds1 or e1 line side loopback for channel n. the receive line side ds1 or e1 clock and data output signals are looped back internally as the ds1 or e1 transmit input signals. the exter- nal ds1 or e1 transmit clock and data input signals are disabled. the ds1 or e1 receive clock and data output signals or line ais are provided at the receive interface, depending on the sate of control bit rnlais (bit 0, x+000h). this control bit works in conjunction with control bit fnlbk (see bit 0 below) to provide a bidirectional loopback. when this control bit and fnlbk are both set to 1, bidirectional loopback is enabled. in this mode of operation, the transmit data is looped back as receive data, and the output of the demapper is looped back as transmit data. the rnclki (bit 3, regis- ter x+000h) and tnclki (bit 3, register x+002h) control bits must be pro- grammed for opposite edges when using line loopback or bidirectional loopback. 0 fnlbk facility loopback: a 1 enables a ds1 or e1 facility (side) loopback for channel n. the ds1 or e1 transmit clock and data output signals are looped back internally as the ds1 or e1 receive clock and data input sig- nals. the external ds1 or e1 receive input signals are disabled. the ds1 or e1 transmit clock and data output signals are provided at the interface. address bit symbol description
temx8 txc-04218 - 164 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+006 7 6 rnlint1 rnlint0 receive line interface selection: the receive line interface for channel n is selected according to the following table: rnlint1 rnlint0 line interface selected 0 0 high z or 0 depending on the state of the rnoutl control bit. 0 1 nrz interface. 1 0 rail interface. b8zs or ami line code for the ds1 line rate. hdb3 or ami line code for the e1 line rate. 1 1 vt/tu interface. 5rnoutl receive line interface high z or 0 selection: enabled only when the rnlint1 and rnlint0 controls bits are set to 00. a 0 forces the line inter- face output signals to a high z state. a 1 forces the line interface output signals to the 0 state. the tu/vt must be selected to drive the receive output low. if using single unidirectional ring mode, forcing outputs to zero state is inhibited. 4 rne1sl receive line rate selection: a 1 selects the e1 line rate for channel n. a 0 selects the ds1 line rate. 3 fnrdis rei and rdi disabled: enabled when the single unidirectional mode (control bits tnsel1, tnsel0 are equal to 01) is selected. a 1 disables receive side alarms or an out of range condition from generating rdi. in addition, the rei value is transmitted as a zero. 2 1 0 rnsel tnsel1 tnsel0 channel n a/b drop/add bus selection: the table below lists the selec- tion criteria for the eight available modes of operation of channel n: tnsel1 tnsel0 rnsel operating mode 0 0 0 a drop only (drop) 0 0 1 b drop only (drop) 0 1 0 a drop a add (single unidirectional ring) 0 1 1 b drop b add (single unidirectional ring) 1 0 0 a drop b add (multiplexer) 1 0 1 b drop a add (multiplexer) 1 1 0 a drop a and b add (dual unidirectional ring) 1 1 1 b drop b and a add (dual unidirectional ring) x+007 7-2 not used: 1tnvtvc transmit vt/tu overhead byte selection: enabled with the vt/tu transmit line interface is selected. a 0 enables the output clock tvtcn to be gapped during the four overhead byte times. a 1 enables the clock to be symmetrical. except for bits 1 and 2 in the k4 byte, the remaining bits in the four overhead bytes are ignored. 0tndisb transmit single bit rdi enable: a 1 configures the a and b add sides for channel n for single bit rdi operation. a 0 configured add channel for three bit rdi. address bit symbol description
temx8 txc-04218 - 165 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+008 7-5 not used: 4rnvtvc receive vt/tu overhead byte selection: enabled with the vt/tu receive line interface is selected. a 0 causes the output clock rvtcn to be gapped during the four overhead byte times. a 1 causes the clock to be symmetrical, and enables the four overhead bytes to be clocked out of the mapper. 3rndien remote defect indication enable: when this bit is set to 1, alarms detected in the a or b drop side vt/tu selected are enabled to send three bit rdi (remote payload, server or connectivity defect indication) or single bit rdi. the alarms for causing rdi are described in the operations section. note: the microprocessor may send an rdi independent of the setting of this control bit. to prevent contention between the internal logic and micro- processor control, this bit should be written with a 0. 2tcnre tandem connection rdi/odi enable: when this bit is set to 1, alarms detected in the a or b drop side vt/tu selected are enabled to send tan- dem connection rdi and odi. the alarms for causing tc rdi and odi are described in the operations section. note: the microprocessor may send an tc rdi (bit 8 in frame 73) or odi (bit 7 in frame 74) independent of the setting of this control bit. to prevent contention between the internal logic and microprocessor control, this bit should be written with a 0. 1rnaise receive line ais enable: when this bit is set to 1, alarms detected in the a or b drop side vt/tu selected are enabled to send receive ds1 or e1 line ais. the alarms for causing received ais to be sent are described in the operations section. note: the microprocessor may send line ais independent of the setting of this control bit. to prevent contention between the internal logic and microprocessor control, this bit should be written with a 0. 0rnsais receive line interface send ais: a 1 forces either a ds1 or e1 line ais signal to be sent in the receive direction independent of the drop side alarms for the vt/tu selected. x+009 7-1 not used: 0 tnreset transmit reset: a 1 clears all performance counters to zero (saturating) or the fe/fffe hex values (8/16 bit non-saturating), and initializes the internal fifos and state machines for the a and b add bus vt/tu channel selected. address bit symbol description
temx8 txc-04218 - 166 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n a side add and drop bus control register descriptions (n = 1 to 8) the following control bits and registers are for the a side drop and add buses. control bits tnsel1, tnsel0 and rnsel determine the drop bus that the data is dropped from, and the add bus(es) data will be added to. the drop side is the receive side, while the add side is the transmit side. address bit symbol description x+010 7-6 not used: 5arntcen a side drop bus channel n tandem connection enable: a 1 enables the a side drop bus tandem connection feature for the vt/tu selected for channel n. a 0 disables the tc feature. please note the tandem connec- tion feature can only be enabled when the j2 byte is configured for a 16 byte message (control bit arnj2s1 is a 0). 4-2 arnsl1 arnsl2 arnsl3 a side drop bus channel n microprocessor written signal label value: the bits written into this register are compared against the received signal for a mismatch signal label detector. the three bit posi- tions correspond to the three signal label bits found in bits 5 through 7 in the v5 byte for the tu/vt selected. bit 4 in this register corresponds to bit 5 in the v5 byte. 1-0 arnj2s1 arnj2s0 a side drop bus channel n j2 byte mode selection: the j2 byte is processed according to the settings in following table. please note: the tandem connection feature for a channel is disabled with the j2 byte is configured for a message size of 64 bytes. arnj2s1 arnj2s0 action 0 0 the j2 memory map segment is configured for 16 byte messages. received bytes are written into this segment on a rotating basis starting with an arbitrary address. the j2 message comparison circuit is disabled. 0 1 the j2 memory map segment is configured for 16 byte messages. received bytes are written into this segment aligned to the multi frame pat- tern. the j2 message comparison circuit is enabled. 1 0 the j2 memory map segment is configured for 64 byte messages. received bytes are written into this segment on a rotating basis starting with an arbitrary address. 1 1 the j2 memory map segment is configured for 64 byte messages. received bytes are written into this segment aligned to cr/lf sequence. the j2 message comparison circuit is disabled. x+011 7-1 not used: 0 dachnr a side drop channel n reset: writing a 1 to this control bit clears all per- formance counters to zero (saturating) or the fe/fffe hex values (8/16 bit non-saturating), and initializes the internal fifos and state machines for the a drop bus vt/tu channel selected. it does not clear the control bit settings, or latched alarms for the channel selected.
temx8 txc-04218 - 167 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+012 7-0 a side drop tu/vt selection a side drop channel n vt/tu selection: the eight-bit binary code writ- ten into this location selects the tu/vt that is to be dropped from the a side drop bus. please refer to the operations section for the description for selecting a vt/tu for a sts-1 in the sts-3 format, and for a tug-3 in the stm-1 vc-4 format. x+01a 7-0 a side add bus tu/vt selection a side add bus channel n tu/vt selection: the eight-bit binary code written into this location selects the tu/vt that is to be added to the a side add bus. please refer to the operations section for the description for selecting a vt/tu for a sts-1 in the sts-3 format, and for a tug-3 in the stm-1 vc-4 format. x+01b 7-0 reserved x+01c to x+05b 7-0 a side add j2 & n2 byte message segments a side add bus channel n j2 and n2 message segments: the follow- ing locations store the transmit 64-byte j2 message when control bit atnj2tsz is a 1, and the transmit microprocessor-written 16-byte j2 mes- sage and 16 byte n2 message when this control bit atnj2tsz is a 0. location message segment 01c-05b transmit j2 message segment (64 bytes). 01c-02b transmit j2 message segment (16 bytes). 02c-03b unused (16 bytes). 03c-04b transmit n2 message segment (16 bytes). 04c-05b unused (16 bytes). x+05c 7-0 a side add bus te s t v 1 byte a side add bus channel n v1 byte: the value written to this location is transmitted as the v1 byte for the vt/tu selected for the a side add bus and when control bit atntptv is a 1. please note: the vt/tu is still sent with a fixed pointer offset. bits 7-0 of the register correspond to bits 1-8 of the v1 byte. x+05d 7-0 a side add bus te s t v 2 byte a side add bus channel n v2 byte: the value written to this location is transmitted as the v2 byte for the vt/tu selected for the a side add bus and when control bit atntptv is a 1. please note: the vt/tu is still sent with a fixed pointer offset. bits 7-0 of the register correspond to bits 1-8 of the v2 byte. x+05e 7-0 a side add bus v4 byte a side add bus channel n v4 byte: the value written to this location is transmitted as the v4 byte for the vt/tu selected for the a side add bus and when control bit atnv4bs is a 1. when control bit atnv4bs is a 0, the v4 byte is transmitted with a 0 value. bits 7-0 of the register corre- spond to bits 1-8 of the v4 byte. x+05f 7-0 a side add bus o-bits a side add bus channel n o bits: the value written to this location is transmitted as the o bits for the vt/tu selected for the a side add bus and when control bit tobwz is 0. bits 7 through 4 correspond to bits 3 through 6 in the first justification control byte. bits 3 through 0 correspond to bits 3 through 6 in the second justification control byte. when control bit tobwz is a 1, the o bits in all channels are transmitted with a value equal to 0. x+060 7-0 a side add bus v5 byte a side add bus channel n v5 byte: the value written to this location is transmitted as the v5 byte for the vt/tu selected for the a side add bus and when control bit atnv5bs (bit 0, register x+064h) is 1. when control bit atnv5bs is set to 0, a normal v5 byte is transmitted. bits 7-0 of the register correspond to bits 1-8 of the v5 byte. address bit symbol description
temx8 txc-04218 - 168 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+061 7-0 a side add bus n2 byte a side add bus channel n n2 byte: the value written to this location is transmitted as the n2 byte for the vt/tu selected for the a side add bus and when control bit atntcen (bit 2, register x+063h) is 0. bits 7-0 of the register correspond to bits 1-8 of the n2 byte. x+062 7-0 a side add bus k4 byte a side add bus channel n k4 byte: the value written to this location is transmitted as the k4 byte for the vt/tu selected for the a side add bus and when control bit atnk4pc (bit 1, register 065h) is 1. when control bit atnk4pc is set to 0, the bits transmitted from this register are a function of the rdi and line interface options. when the three bit rdi feature is enabled, the values in bits 5, 6, and 7 are ignored. when the single bit rdi feature is enabled, bits 5, 6, and 7 from this register are transmitted. when the vt symmetrical clock interface is enabled, bits 1 and 2 in this register are ignored. bits 3, 4, and 8 are always transmitted from this register. bits 7-0 of the register correspond to bits 1-8 of the k4 byte. x+063 7 atntcais a side add bus channel n transmit tandem connection ais: enabled when control bit atntcen is a 1. a 1 causes bit 4 in the n2 byte to be transmitted as a 1. 6atngais a side add bus channel n transmit vt/tu ais: a 1 enables a tu/vt ais to be transmitted for the tu/vt selected for the a side add bus. a tu/vt ais consists of all ones in the entire tu/vt, including the v1 through v4 bytes. 5 atntptv a side add bus channel n transmit vt/tu v1/v2 test pointer bytes: a 1 enables the test pointer value written to registers x+05ch (v1 byte) and x+05dh (v2 byte) by the microprocessor to be transmitted. please note that the pointer offset for the overhead bytes (e.g., v5 byte) and the payload will remain fixed. address bit symbol description
temx8 txc-04218 - 169 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+063 (cont.) 4anuqge a side add bus channel n unequipped channel generation: this control bit works in conjunction with the anuqsu control bit according to the following table: anuqge anuqsu action 0 x normal operation. 1 0 unequipped tu/vt generated. an unequipped vt/tu consists of a normal ndf, size bits equal to 10 (vt2/tu-12) or 11 (vt1.5/tu-11), a fixed pointer equal to 105 (vt2/tu-12) or 78 (vt1.5/tu-11), and all other bytes equal to 00h. 1 1 unequipped supervisory vt/tu generated. an unequipped supervisory tu/vt consists of a nor- mal ndf, size bits equal to 10 (vt2/tu-12) or 11 (vt1.5/tu-11), a fixed pointer equal to 105 (vt2/tu-12) or 78 (vt1.5/tu-11), and a valid j2 byte. the v5 byte will consist of a valid bip-2, sig- nal label set to 0. the n2 byte will be sent as zero. the rdi bits, v5 bit 8 and k4 bits 5, 6 and 7 will be controlled by the microprocessor and the payload will set to zeros. note: x = don?t care (0 or 1). 3anuqsu a side add bus channel n unequipped supervisory channel enabled: works in conjunction with the anuqge control bit according to the table given above. 2 atntcen a side add bus channel n tandem connection enable: works in con- junction with the atnj2tsz bit according to the following table: atntcen atnj2tsz action 0 x tandem connection feature is disabled. the n2 byte transmitted is the microprocessor writ- ten value at register x+061h. 1 0 tandem connection feature is enabled. the j2 64 byte message ram segment is used on a shared basis. the transmit j2 message and n2 byte are configured for 16-byte message sizes. 1 1 the j2 message segment is configured for a 64 message size. the single byte microprocessor written value is repeated and transmitted 16 times along with the multiframe alignment pat- tern, and tc odi and tc rdi. note: x = don?t care (0 or 1). address bit symbol description
temx8 txc-04218 - 170 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+063 (cont.) 1 atnj2ten a side add bus channel n transmit j2 message type: works in con- junction with the atnj2tsz bit according to the following table: atnj2ten atnj2tsz action 0 0 transmit j2 message segment configured for a 16-byte message size. 0 1 transmit j2 message segment configured for a 64-byte message size. 1 x j2 message segment transmitted as 00h. note: x = don?t care (0 or 1). 0 atnj2tsz a side add bus channel n transmit j2 message size segment: works in conjunction with the atnj2ten bit according to the table described above. x+064 7 atnrfi a side add bus channel n transmit rfi (remote failure indication): a 1 causes the rfi bit (bit 4 in the v5 byte) to be transmitted as a 1. a 0 transmits this bit as a 0. 6 atnrdip a side add bus channel n transmit remote payload defect indica- tion: enabled only for three bit rdi operation (control bit tndisb is set to 0). a 1 transmits a remote payload defect indication (bits 5, 6, and 7 in the k4 byte equals 010, and bit 8 in the v5 equals 0) independent of the alarms. 5 atnrdic a side add bus channel n transmit remote connectivity defect indication: enabled only for three bit rdi operation (control bit tndisb is set to 0). a 1 transmits a remote connectivity defect indication (bits 5, 6, and 7 in the k4 byte equals 110, and bit 8 in the v5 equals 1) independent of the alarms. 4 atnrdis a side add bus channel n transmit remote server defect indication or single bit rdi: for three bit rdi operation (control bit tndisb is set to 0), a 1 transmits a remote server defect indication (bits 5, 6, and 7 in the k4 byte equals 101, and bit 8 in the v5 equals 1) independent of the alarms. for single bit rdi operation, a 1 transmit a remote defect indica- tion (bit 8 in the v5 equals 1). 3 atnfb2 a side add bus channel n transmit bip-2 error: a 1 causes bits 1 and 2 (the bip-2 value) in the v5 byte to be inverted from the calculated value and transmitted for one frame. to send another error, this bit must be writ- ten with a 0 followed by a 1. 2 atntcuq a side add bus channel n transmit tc unequipped status: enabled when control bit atntcen is a 1. a 1 causes bits a tc unequipped byte to be transmitted. 1 not used: 0 atnv5bs a side add bus channel n transmit v5 byte register value: a 1 enables the microprocessor written v5 byte value at register x+060h to be transmitted. address bit symbol description
temx8 txc-04218 - 171 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+065 7 not used: 6 atnffb a side add bus channel n transmit rei error: a 1 causes bit 3 (rei) of the v5 byte to be transmitted as a 1 for one multiframe. to send another error, this bit must be written with a 0 followed by a 1. please note that if a febe is being sent as a result of a receive bip-2 error, the rei error set by this bit is transmitted afterwards. 5 4 3 atnsl1 atnsl2 atnsl3 a side add bus channel n transmit microprocessor written signal label value: the value written into this field is sent as the signal label in the v5 byte. the three bit positions correspond to the three signal label bits found in bits 5 through 7 in the v5 byte for the tu/vt selected. bit 5 in this register corresponds to bit 5 in the v5 byte. 2 not used: 1 atnk4pc a side add bus channel n transmit k4 byte register value: a 1 enables the microprocessor written value for the k4 byte to be transmitted. when set to 0, 3-bit rdi controls bits 5 - 7 when enabled, and the vt inter- face controls bits 1 and 2 when enabled and the symmetrical clock output is selected. otherwise these bits are sourced from the microprocesor writ- ten value. bits 3, 4, 8 are always sourced from the microprocessor written value. 0anhighz a side add bus channel n force high impedance for the vt/tu selected: a 1 forces the time slots corresponding to the vt/tu selected to the high impedance state. x+066 7-3 not used: 2 atntcso a side add bus channel n transmit tandem connection odi: enabled when control bit atntcen is a 1. a 1 causes bit 7 in frame 74 in the n2 byte to be transmitted as a 1 independent of tc alarms. 1 atntcsr a side add bus channel n transmit tandem connection rdi: enabled when control bit atntcen is a 1. a 1 causes bit 8 in frame 73 in the n2 byte to be transmitted as a 1 independent of tc alarms. 0 atnv4bs a side add bus channel n transmit v4 byte register value: a 1 enables the microprocessor written value for the v4 byte to be transmitted. when set to 0, the transmitted v4 byte value is 00h. address bit symbol description
temx8 txc-04218 - 172 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side desynchronizer register description (n = 1 to 8) address bit symbol description x+017 7-0 a drop pointer leak rate value (bit 7-0) a side drop bus channel n desynchronizer pointer leak rate reg- ister bits 7-0: this register contains the first 8 bits in a 10 bit pointer leak register. the value written into this location and the next location is used for the internal leak rate buffer, and represents the average leak rate based on a count. a count of one represents 8 frames, or 2 multi- frames, between bits leaked. bit 0 is the lsb. note: if the 10 bit register is set to 0 the pointer leak buffer in the desyn- chronizer is bypassed. the following alarms will cause the contents of locations x+017h and x+018h to be reset to their default values: anlop, anais, a1uais, a2uais, a3uais or a1hlom, a2hlom, or a3hlom. following these alarms, 3 rising edges of pm1s are required before x+017h and x+018h can be written to. x+018 7-2 not used: 1-0 a drop pointer leak rate value (bits 9-8) a side drop bus channel n desynchronizer pointer leak rate reg- ister bits 9-8: this register contains the last two bits in a 10 bit pointer leak register. the value written into this location along with the register is used for the internal leak rate buffer, and represents the average leak rate based on a count. a count of one represents 8 frames, or 2 multi- frames, between bits leaked. bit 9 is the msb. note: if the 10 bit register is set to 0 the pointer leak buffer in the desyn- chronizer is bypassed.
temx8 txc-04218 - 173 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side add and drop bus control register descriptions (n = 1 to 8) the following control bits and registers are for the a side drop and add buses. control bits tnsel1, tnsel0 and rnsel determine the drop bus that the data is dropped from, and the add bus(es) data will be added to. the drop side is the receive side, while the add side is the transmit side. address bit symbol description x+080 7-6 not used: 5brntcen b side drop bus channel n tandem connection enable: a 1 enables the b side drop bus tandem connection feature for the vt/tu selected for channel n. a 0 disables the tc feature. please note the tandem connec- tion feature can only be enabled when the j2 byte is configured for a 16 byte message. 4-2 brnsl1 brnsl2 brnsl3 b side drop bus channel n microprocessor written signal label value: the bits written into this register are compared against the received signal for a mismatch signal label detector. the three bit posi- tions correspond to the three signal label bits found in bits 5 through 7 in the v5 byte for the tu/vt selected. bit 4 in this register corresponds to bit 5 in the v5 byte. 1-0 brnj2s1 brnj2s0 b side drop bus channel n j2 byte mode selection: the j2 byte is processed according to the settings in following table. please note: the tandem connection feature for a channel is disabled with the j2 byte is configured for a message size of 64 bytes. brnj2s1 brnj2s0 action 0 0 the j2 memory map segment is configured for 16 byte messages. received bytes are written into this segment on a rotating basis starting with an arbitrary address. the j2 message comparison circuit is disabled. 0 1 the j2 memory map segment is configured for 16 byte messages. received bytes are written into this segment aligned to the multi frame pat- tern. the j2 message comparison circuit is enabled. 1 0 the j2 memory map segment is configured for 64 byte messages. received bytes are written into this segment on a rotating basis starting with an arbitrary address. 1 1 the j2 memory map segment is configured for 64 byte messages. received bytes are written into this segment aligned to cr/lf sequence. the j2 message comparison circuit is disabled. x+081 7-1 not used: 0 dbchnr b side drop channel n reset: writing a 1 to this control bit clears all per- formance counters to zero (saturating) or the fe/fffe hex values (8/16 bit non-saturating), and initializes the internal fifos and state machines for the b drop bus vt/tu channel selected. it does not clear the control bit settings, or latched alarms for the channel selected.
temx8 txc-04218 - 174 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+082 7-0 b side drop tu/vt selection b side drop channel n vt/tu selection: the eight-bit binary code writ- ten into this location selects the tu/vt that is to be dropped from the b side drop bus. please refer to the operations section for the description for selecting a vt/tu for a sts-1 in the sts-3 format, and for a tug-3 in the stm-1 vc-4 format. x+08a 7-0 b side add bus tu/vt selection b side add bus channel n tu/vt selection: the eight-bit binary code written into this location selects the tu/vt that is to be added to the b side add bus. please refer to the operations section for the description for selecting a vt/tu for a sts-1 in the sts-3 format, and for a tug-3 in the stm-1 vc-4 format. x+08b 7-0 reserved x+08c to x+0cb 7-0 b side add j2 & n2 byte message segments b side add bus channel n j2 and n2 message segments: the follow- ing locations store the transmit 64-byte j2 message when control bit btnj2tsz is a 1, and the transmit microprocessor-written 16-byte j2 message and 16 byte n2 message when this control bit btnj2tsz is a 0. location message segment 08c-0cb transmit j2 message segment (64 bytes). 08c-09b transmit j2 message segment (16 bytes). 09c-0ab unused (16 bytes). 0ac-0bb transmit n2 message segment (16 bytes). 0bc-0cb unused (16 bytes). x+0cc 7-0 b side add bus te s t v 1 byte b side add bus channel n v1 byte: the value written to this location is transmitted as the v1 byte for the vt/tu selected for the b side add bus and when control bit btntptv is a 1. please note: the vt/tu is still sent with a fixed pointer offset. bits 7-0 of the register correspond to bits 1-8 of the v1 byte. x+0cd 7-0 b side add bus te s t v 2 byte b side add bus channel n v2 byte: the value written to this location is transmitted as the v2 byte for the vt/tu selected for the b side add bus and when control bit btntptv is a 1. please note: the vt/tu is still sent with a fixed pointer offset. bits 7-0 of the register correspond to bits 1-8 of the v2 byte. x+0ce 7-0 b side add bus v4 byte b side add bus channel n v4 byte: the value written to this location is transmitted as the v4 byte for the vt/tu selected for the b side add bus and when control bit btnv4bs is a 1. when control bit btnv4bs is a 0, the v4 byte is transmitted with a 0 value. bits 7-0 of the register corre- spond to bits 1-8 of the v4 byte. x+0cf 7-0 b side add bus o-bits b side add bus channel n o bits: the value written to this location is transmitted as the o bits for the vt/tu selected for the b side add bus and when control bit tobwz is 0. bits 7 through 4 correspond to bits 3 through 6 in the first justification control byte. bits 3 through 0 correspond to bits 3 through 6 in the second justification control byte. when control bit tobwz is a 1, the o bits in all channels are transmitted with a value equal to 0. x+0d0 7-0 b side add bus v5 byte b side add bus channel n v5 byte: the value written to this location is transmitted as the v5 byte for the vt/tu selected for the b side add bus and when control bit btnv5bs (bit 0, register x+0d4h) is 1. when control bit btnv5bs is set to 0, a normal v5 byte is transmitted. bits 7-0 of the register correspond to bits 1-8 of the v5 byte. address bit symbol description
temx8 txc-04218 - 175 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+0d1 7-0 b side add bus n2 byte b side add bus channel n n2 byte: the value written to this location is transmitted as the n2 byte for the vt/tu selected for the b side add bus and when control bit atntcen (bit 2, register x+0d3h) is 0. bits 7-0 of the register correspond to bits 1-8 of the n2 byte. x+0d2 7-0 b side add bus k4 byte b side add bus channel n k4 byte: the value written to this location is transmitted as the k4 byte for the vt/tu selected for the b side add bus and when control bit btnk4pc (bit 1, register 0d5h) is 1. when control bit btnk4pc is set to 0, the bits transmitted from this register are a function of the rdi and line interface options. when the three bit rdi feature is enabled, the value in bits 5, 6, and 7 are ignored. when the single bit rdi feature is enabled, bits 5, 6, and 7 from this register are transmitted. when the vt symmetrical clock interface is enabled, bits 1 and 2 in this register are ignored. bits 3, 4, and 8 are always transmitted from this register. bits 7-0 of the register correspond to bits 1-8 of the k4 byte. x+0d3 7 btntcais b side add bus channel n transmit tandem connection ais: enabled when control bit btntcen is a 1. a 1 causes bit 4 in the n2 byte to be transmitted as a 1. 6btngais b side add bus channel n transmit vt/tu ais: a 1 enables a tu/vt ais to be transmitted for the tu/vt selected for the b side add bus. a tu/vt ais consists of all ones in the entire tu/vt, including the v1 through v4 bytes. 5 btntptv b side add bus channel n transmit vt/tu v1/v2 test pointer bytes: a 1 enables the test pointer value written to registers x+0cch (v1 byte) and x+0cdh (v2 byte) by the microprocessor to be transmitted. please note that the pointer offset for the overhead bytes (e.g., v5 byte) and the payload will remain fixed. address bit symbol description
temx8 txc-04218 - 176 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+0d3 (cont.) 4 bnuqge b side add bus channel n unequipped channel generation: this control bit works in conjunction with the bnuqsu control bit according to the following table: b n uq g e bn uq s u a ction 0 x normal operation. 1 0 unequipped tu/vt generated. an unequipped vt/tu consists of a normal ndf, size bits equal to 10 (vt2/tu-12) or 11 (vt1.5/tu-11), a fixed pointer equal to 105 (vt2/tu-12) or 78 (vt1.5/tu-11), and all other bytes equal to 00h. 1 1 unequipped supervisory vt/tu generated. an unequipped supervisory tu/vt consists of a nor- mal ndf, size bits equal to 10 (vt2/tu-12) or 11 (vt1.5/tu-11), a fixed pointer equal to 105 (vt2/tu-12) or 78 (vt1.5/tu-11), and a valid j2 byte. the v5 byte will consist of a valid bip-2, sig- nal label set to 0. the n2 byte will be sent as zero. the rdi bits, v5 bit 8 and k4 bits 5, 6 and 7 will be controlled by the microprocessor and the payload will set to zeros. note: x = don?t care (0 or 1). 3bnuqsu b side add bus channel n unequipped supervisory channel enabled: works in conjunction with the bnuqge control bit according to the table given above. 2 btntcen b side add bus channel n tandem connection enable: works in con- junction with the btnj2tsz bit according to the following table: btntcen btnj2tsz action 0 x tandem connection feature is disabled. the n2 byte transmitted is the microprocessor writ- ten value at register x+0d1h. 1 0 tandem connection feature is enabled. the j2 64 byte message ram segment is used on a shared basis. the transmit j2 message and n2 byte are configured for 16-byte message sizes. 1 1 the j2 message segment is configured for a 64 message size. the single byte microprocessor written value is repeated and transmitted 16 times along with the multiframe alignment pat- tern, and tc odi and tc rdi. note: x = don?t care (0 or 1). address bit symbol description
temx8 txc-04218 - 177 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+0d3 (cont.) 1 btnj2ten b side add bus channel n transmit j2 message type: works in con- junction with the btnj2tsz bit according to the following table: btnj2ten btnj2tsz action 0 0 transmit j2 message segment configured for a 16-byte message size. 0 1 transmit j2 message segment configured for a 64-byte message size. 1 x j2 message segment transmitted as 00h. note: x = don?t care (0 or 1). 0 btnj2tsz b side add bus channel n transmit j2 message size segment: works in conjunction with the btnj2ten bit according to the table described above. x+0d4 7 btnrfi b side add bus channel n transmit rfi (remote failure indication): a 1 causes the rfi bit (bit 4 in the v5 byte) to be transmitted as a 1. a 0 transmits this bit as a 0. 6btnrdip b side add bus channel n transmit remote payload defect indica- tion: enabled only for three bit rdi operation (control bit tndisb is set to 0). a 1 transmits a remote payload defect indication (bits 5, 6, and 7 in the k4 byte equals 010, and bit 8 in the v5 equals 0) independent of the alarms. 5 btnrdic b side add bus channel n transmit remote connectivity defect indication: enabled only for three bit rdi operation (control bit tndisb is set to 0). a 1 transmits a remote connectivity defect indication (bits 5, 6, and 7 in the k4 byte equals 110, and bit 8 in the v5 equals 1) independent of the alarms. 4btnrdis b side add bus channel n transmit remote server defect indication or single bit rdi: for three bit rdi operation (control bit tndisb is set to 0), a 1 transmits a remote server defect indication (bits 5, 6, and 7 in the k4 byte equals 101, and bit 8 in the v5 equals 1) independent of the alarms. for single bit rdi operation, a 1 transmit a remote defect indica- tion (bit 8 in the v5 equals 1). 3 btnfb2 b side add bus channel n transmit bip-2 error: a 1 causes bits 1 and 2 (the bip-2 value) in the v5 byte to be inverted from the calculated value and transmitted for one frame. to send another error, this bit must be writ- ten with a 0 followed by a 1. 2 btntcuq b side add bus channel n transmit tc unequipped status: enabled when control bit btntcen is a 1. a 1 causes bits a tc unequipped byte to be transmitted. 1 not used: 0 btnv5bs b side add bus channel n transmit v5 byte register value: a 1 enables the microprocessor written v5 byte value at register x+0d0h to be transmitted. address bit symbol description
temx8 txc-04218 - 178 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+0d5 7 not used: 6 btnffb b side add bus channel n transmit rei error: a 1 causes bit 3 (rei) of the v5 byte to be transmitted as a 1 for one multiframe. to send another error, this bit must be written with a 0 followed by a 1. please note that if a rei count is being sent as a result of a receive bip-2 error, the rei error set by this bit is transmitted afterwards. 5 4 3 btnsl1 btnsl2 btnsl3 b side add bus channel n transmit microprocessor written signal label value: the value written into this field is sent as the signal label in the v5 byte. the three bit positions correspond to the three signal label bits found in bits 5 through 7 in the v5 byte for the tu/vt selected. bit 5 in this register corresponds to bit 5 in the v5 byte. 2 not used: 1btnk4pc b side add bus channel n transmit k4 byte register value: a 1 enables the microprocessor written value for the k4 byte to be transmitted. when set to 0, 3-bit rdi controls bits 5 - 7 when enabled, and the vt interface controls bits 1 and 2 when enabled an d the symmetrical clock output is selected. otherwise, these bits are s ourced from the microprocessor written value. bits 3, 4 and 8 are always sourced from the microprocessor written value. 0bnhighz b side add bus channel n force high impedance for the vt/tu selected. a 1 forces the time slots corresponding to the vt/tu selected to the high impedance state. x+0d6 7-3 not used: 2 btntcso b side add bus channel n transmit tandem connection odi: enabled when control bit btntcen is a 1. a 1 causes bit 7 in frame 74 in the n2 byte to be transmitted as a 1 independent of tc alarms. 1 btntcsr b side add bus channel n transmit tandem connection rdi: enabled when control bit btntcen is a 1. a 1 causes bit 8 in frame 73 in the n2 byte to be transmitted as a 1 independent of tc alarms. 0 btnv4bs b side add bus channel n transmit v4 byte register value: a 1 enables the microprocessor written value for the v4 byte to be transmitted. when set to 0, the transmitted v4 byte value is 00h. address bit symbol description
temx8 txc-04218 - 179 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side desynchronizer register description (n = 1 to 8) channel n - a and b side add bus alarm mask bits (n = 1 to 8) address bit symbol description x+087 7-0 b drop pointer leak rate value (bit 7-0) b side drop bus channel n desynchronizer pointer leak rate reg- ister bits 7-0: this register contains the first 8 bits in a 10 bit pointer leak register. the value written into this location and the next location is used for the internal leak rate buffer, and represents the average leak rate based on a count. a count of one represents 8 frames, or 2 multi- frames, between bits leaked. bit 0 is the lsb. note: if the 10 bit register is set to 0 the pointer leak buffer in the desyn- chronizer is bypassed. the following alarms will cause the contents of locations x+087h and x+088h to be reset to their default values: bnlop, bnais, b1uais, b2uais, b3uais or b1hlom, b2hlom, or b3hlom. following these alarms, 3 rising edges of pm1s are required before x+087h and x+088h can be written to. x+088 7-2 not used: 1-0 b drop pointer leak rate value (bits 9-8) b side drop bus channel n desynchronizer pointer leak rate reg- ister bits 9-8: this register contains the last two bits in a 10 bit pointer leak register. the value written into this location along with the register is used for the internal leak rate buffer, and represents the average leak rate based on a count. a count of one represents 8 frames, or 2 multi- frames, between bits leaked. bit 9 is the msb. note: if the 10 bit register is set to 0 the pointer leak buffer in the desyn- chronizer is bypassed. address bit symbol description x+005 7-6 not used: 5mntais transmit channel n line ais alarm mask bit: a 1 enables the hard- ware interrupt for a line ais for channel n. 4 mnbtfe transmit b side add bus channel n fifo error indication mask bit: a 1 enables the hardware interrupt for a b side fifo error indication for channel n. 3 mnatfe transmit a side add bus channel n fifo error indication mask bit: a 1 enables the hardware interrupt for a a side fifo error indication for channel n. 2mnool channel n test analyzer out of lock alarm mask bit: a 1 enables the hardware interrupt for a test analyzer out of lock alarm for channel n. 1 mntlos transmit channel n loss of signal alarm mask bit: a 1 enables the hardware interrupt for a transmit loss of signal alarm for channel n. 0 mntloc transmit channel n loss of clock alarm mask bit: a 1 enables the hardware interrupt for a transmit loss of clock alarm for channel n.
temx8 txc-04218 - 180 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a and b side add bus status register and counter descriptions the following descriptions pertain to the status registers and counters assigned to channel n. the status regis- ters provide four readable bit positions per alarm. the alarm status are provided as unlatched alarm indica- tions, latched alarm indications, one second indications, and previous one second indications. the counters provide three readable counters per counter. the counters are provided as current count, previous second bit (in the preceding even-numbered address) provides the alarm status as an latched alarm indication. a latched bit position is set on positive, negative, or both positive and negative transitions of the alarm. a latched alarm is cleared on a microprocessor read cycle of its address. during a read cycle for a counter, internal logic holds any increment to the counter until the read cycle is complete, and then updates the counter afterwards. address bit symbol description x+100 7-6 not used: 5tnais transmit channel n line ais alarm indication: line ais is defined as an unframed all ones signal. a 1 indicates that line ais has been detected. a ds1 ais is declared when 99.9% or more ones are detected in the signal in a period of 48 ms. recovery occurs when the line signal ansi has fewer then 99.9% of ones in a 48 ms period. for the e1 line rate, ais is declared when line signal has two or less zeros in each of two consecutive double frame periods (four frames). recovery occurs when each of the two consecutive double frame peri- ods contain three or more zeros. other than reporting the alarm, no action is taken. other than reporting the alarm, no action is taken. 4tbnffe transmit b add bus channel n fifo error indication: a 1 indicates that the b add bus fifo has overflowed or underflowed. the fifo is recentered and is held reset for up to two multiframes automatically. vt/tu ais is transmitted for the vt/tu and bus selected for up to two multiframes when a fifo error occurs. 3 tanffe transmit a add bus channel n fifo error indication: a 1 indicates that the a add bus fifo has overflowed or underflowed. the fifo is recentered and is held reset for up to two multiframes automatically. vt/tu ais is transmitted for the vt/tu and bus selected for up to two multiframes when a fifo error occurs. 2 cnool channel n test analyzer out of lock alarm: enabled when control bit tnanz is a 1. an analyzer out of lock is declared when there is a mis- match in the prbs pattern recovery occurs when: the data is in lock for 25 clock cycles for the 2 15 +1 prbs pattern. the data is in lock for 32 clock cycles for the 2 20 +1 prbs pattern.
temx8 txc-04218 - 181 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+100 (cont.) 1 tnlos transmit channel n loss of signal alarm: the loss of signal detector is enabled for the rail interface only. a ds1 loss of signal is declared when there are no signal transitions detected on the positive rail and the negative rail for a period of 175 +/- 75 consecutive pulse positions. recovery occurs when the average pulse density of at least 12.5% occurs over a period of 175 +/- 75 consecutive pulse positions. a loss of signal alarm for the e1 line rate alarm is declared when there are no signal transitions detected on the positive rail and the negative rail for a period of 256 consecutive pulse positions. recovery occurs when there are at least 32 transitions counted for 256 consecutive pulse positions. when the nrz interface is selected, a external loss of signal may be inputted using the negative rail lead when control bit exnlos is a 1. the input sense is determined by control bit exnlosp. when control bit exnlosp is a 1, the loss of signal indication should be active high. 0tnloc transmit channel n loss of clock alarm: a 1 indicates that the trans- mit clock (tcin) for port n has stuck high or low for 6 or more clock cycles. recovery occurs on the first clock transition. x+101 7-6 not used: 5ltnais transmit channel n line ais latched alarm indication: this bit posi- tion latches for a transmit line ais alarm indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 4 ltbnffe transmit channel n b side add bu s fifo latched alarm indication: this bit position latches for a transmit b side add bus fifo alarm indica- tion. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3ltanffe transmit channel n a side add bu s fifo latched alarm indication: this bit position latches for a transmit a side add bus fifo alarm indica- tion. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2 lcnool channel n test analyzer out of lock latched alarm: this bit posi- tion latches for a prbs analyzer out of lock alarm indication. this bit is set on either a positive transition, negative transition or positive and neg- ative alarm transition. this bit is cleared on a read cycle. note that the only resets which operate on this bit are the reset lead and the soft- ware reset (reseth). 1 ltnlos transmit channel n loss of signal latched alarm indication: this bit position latches for a transmit loss of signal alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0 ltnloc transmit channel n loss of clock latched alarm indication: this bit position latches for a transmit loss of clock alarm indication. this bit is set on either a positive transition, negative transition or positive and neg- ative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 182 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+103 7-6 not used: 5ptnais transmit channel n line ais one second alarm indication: this bit position is set when the transmit ais alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 4 ptbnffe transmit channel n b side add bus fifo one second alarm indi- cation: this bit position is set when the transmit b side add bus fifo alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3 ptanffe transmit channel n a side add bus fifo one second alarm indi- cation: this bit position is set when the transmit a side add bus fifo alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2pcnool channel n test analyzer out of lock one second alarm: this bit position is set when the prbs test analyzer out of lock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1 ptnlos transmit channel n loss of signal one second alarm indication: this bit position is set when the transmit loss of signal alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0 ptnloc transmit channel n loss of clock one second alarm indication: this bit position is set when the transmit loss of clock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 183 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+104 7-6 not used: 5ftnais transmit channel n line ais persistent one second alarm indica- tion: this bit position is set to 1 for the one-second interval, when the transmit line ais alarm indication is active, but did not become active in the previous one second interval. 4 ftbnffe transmit channel n b side add bus fifo persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the transmit b side add bus fifo alarm indication is active, but did not become active in the previous one second interval. 3 ftanffe transmit channel n a side add bus fifo persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the transmit a side add bus fifo alarm indication is active, but did not become active in the previous one second interval. 2fcnool channel n test analyzer out of lock persistent one second alarm: this bit position is set to 1 for the one-second interval, when the prbs test analyzer out of lock alarm indication is active, but did not become active in the previous one second interval. 1ftnlos transmit channel n loss of signal persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the transmit loss of clock alarm indication is active, but did not become active in the previous one second interval. 0 ftnloc transmit channel n loss of clock persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the transmit loss of clock alarm indication is active, but did not become active in the previous one second interval. x+105 7-0 transmit coding violation counter (7-0) transmit channel n coding violation counter - low order byte: low order byte of a 16-bit counter which counts the number of coding errors that have occurred in the ds1 b8zs or e1 hdb3 line code. this low order byte must be read before the high order byte for the same channel is read, which is located in the following address. x+106 7-0 transmit coding violation counter (15-8) transmit channel n coding violation counter - high order byte: high order byte of an 16 counter which counts the number of coding errors that have occurred in the ds1 b8zs or e1 hdb3 line codes. this high order byte must be read after the low order byte for the same chan- nel, which is located in the preceding address, but before the next read of the low order byte for any channel. x+107 7-0 transmit coding violation previous 1 second counter (7-0) transmit channel n previous one second coding violation counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for coding violation counts that occurred in the previous one second interval. this location is updated from the coding violation counter at one second intervals. address bit symbol description
temx8 txc-04218 - 184 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side drop bus alarm mask bits (n = 1 to 8) x+108 7-0 transmit coding violation previous 1 second counter (15-8) transmit channel n previous one second coding violation counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for coding violation counts that occurred in the previous one second interval. this location is updated from the coding violation counter at one second intervals. x+109 7-0 transmit coding violation current 1 second counter (7-0) transmit channel n current one second coding violation counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for coding violation counts that occurred in the current one second inter- val. this location is updated from the coding violation counter at one second intervals. x+10a 7-0 transmit coding violation current 1 second counter (15-8) transmit channel n current one second coding violation counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for coding violation counts that occurred in the current one sec- ond interval. this location is updated from the coding violation counter at one second intervals. address bit symbol description x+013 7 not used: 6manvais a side drop bus channel n vc ais alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side drop bus vc ais latched bit alarm indication for channel n. 5manuqe a side drop bus channel n unequipped indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side unequipped latched bit alarm indication for channel n. 4 manrdic a side drop bus channel n remote connectivity defect indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side remote connectivity defect latched bit alarm indication for channel n. 3manrdip a side drop bus channel n remote payload defect indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side remote payload defect latched bit alarm indication for channel n. address bit symbol description
temx8 txc-04218 - 185 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+013 (cont.) 2manrdis a side drop bus channel n remote server defect indication or sin- gle bit rdi alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side remote server defect or single bit rdi latched bit alarm indication for channel n. 1 mansler a side drop bus channel n signal label mismatch alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side signal label alarm latched bit alarm indication for channel n. 0manrfi a side drop bus channel n remote failure indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side remote failure indication alarm for channel n. x+014 7-5 not used: 4manrfe a side drop bus channel n fifo error indication mask bit: setting this bit to 1 a 1 enables the hardware interrupt for a a side fifo error indi- cation latched bit alarm indication for channel n. 3 manais a side drop bus channel n vt/tu ais alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side vt/tu ais alarm latched bit alarm indication for channel n. 2manlop a side drop bus channel n vt/tu loss of pointer alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side loss of pointer alarm latched bit alarm indication for channel n. 1manndf a side drop bus channel n vt/tu new data flag indication indica- tion mask bit: setting this bit to 1 enables the hardware interrupt for a a side ndf latched bit indication for channel n. 0 mansize a side drop bus channel n vt/tu incorrect pointer size indication mask bit: setting this bit to 1 enables the hardware interrupt for a a side vt/tu incorrect pointer latched bit indication for channel n. x+015 7-2 not used: 1manj2tim a side drop bus channel n j2 loss of lock alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side j2 loss of lock alarm latched bit indication for channel n. 0manj2lol a side drop bus channel n j2 trail trace mismatch alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side j2 mis- match alarm latched bit indication for channel n. x+016 7 mantclm a side drop bus channel n tandem connection loss of multiframe alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side tc loss of multiframe alarm latched bit indication for channel n. 6mantcll a side drop bus channel n tandem connection loss of lock alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side tc loss of lock alarm latched bit indication for channel n. 5 mantctm a side drop bus channel n tandem connection trail trace message alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side tc mismatch alarm latched bit indication for channel n. address bit symbol description
temx8 txc-04218 - 186 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side drop status register descriptions (n = 1 to 8) the following descriptions pertain to the status registers assigned to channel n for the a side drop bus. the status registers provide four readable bit positions per alarm. the alarm status are provides as unlatched alarm indications, latched alarm indications, one second indications, and previous one second indications. the latched bit position is set on positive, negative, or both positive and negative transitions of the alarm. a latched alarm is cleared on a microprocessor read cycle of its address. x+016 (cont.) 4 mantcais a side drop bus channel n tandem connection ais alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side tc ais alarm latched bit indication for channel n. 3 mantcuq a side drop bus channel n tandem connection unequipped alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side tc unequipped alarm latched bit indication for channel n. 2mant- crdi a side drop bus port n tandem connection rdi alarm mask bit: set- ting this bit to 1 enables the hardware interrupt for a a side tc rdi alarm latched bit indication for channel n. 1mant- codi a side drop bus channel n tandem connection odi alarm mask bit: setting this bit to 1 enables the hardware interrupt for a a side tc odi alarm latched bit indication for channel n. 0 not used: address bit symbol description x+110 7 not used: 6anvcais a side drop bus channel n vc ais (unlatched) detected: a vc ais state is defined as a signal label equal to 111 (bits 5-7 in v5 byte). a 1 indicates that an vc ais has been detected in the v5 signal label for the tu/vt selected for five or more consecutive received vc ais signal labels. recovery occurs when five or more consecutive signal labels are received not equal to 111. 5anuneq a side drop bus channel n unequipped indication (unlatched) detected: a 1 indicates that an unequipped status has been detected in the v5 signal label (bits 5-7 in v5 byte are equal to 000) for the tu/vt selected for five or more consecutive received unequipped signal labels. recovery occurs when five or more consecutive signal labels are received not equal to 000. 4 anrdic a side drop bus channel n remote connectivity defect indication (unlatched) detected: a 1 indicates that a remote connectivity defect alarm has been detected. the number of consecutive events used for detection and recovery is determined by control bit v5al10. address bit symbol description
temx8 txc-04218 - 187 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+110 (cont.) 3anrdip a side drop bus channel n remote payload defect indication (unlatched) detected: a 1 indicates that a remote payload defect alarm has been detected. the number of consecutive events used for detec- tion and recovery is determined by control bit v5al10. 2anrdis a side drop bus channel n remote server defect indication or sin- gle bit rdi (unlatched) detected: a 1 indicates that a remote server defect alarm or a single bit rdi state has been detected. the number of consecutive events used for detection and recovery is determined by control bit v5al10. 1 ansler a side drop bus channel n signal label mismatch detected (unlatched): a 1 indicates that the dropped signal label (bits 5-7 in v5 byte) for the vt/tu selected does not match the microprocessor-written signal label for five or more consecutive events. recovery occurs when five or more consecutive correct signal labels are detected. 0anrfi a side drop bus channel n remote failure indication detected (unlatched): a 1 indicates that bit 4 in the v5 byte is equal to 1 for the vt/tu selected. the detection and recovery time is five consecutive multiframes. x+111 7-5 not used: 4 anrffe a side drop bus channel n fifo error (unlatched): a 1 indicates that the receive fifo in the desynchronizer for channel n has overflowed or underflowed for the vt/tu selected. the fifo is reset automatically. line ais will be sent for two multiframes when enabled. 3anais a side drop bus channel n vt/tu ais detected (unlatched): a 1 indicates that a ais state has been detected in the v1/v2 pointer bytes for the vt/tu selected. 2anlop a side drop bus channel n vt/tu loss of pointer detected (unlatched): a 1 indicates that a loss of pointer (lop) has been detected in the v1/v2 pointer bytes for the vt/tu selected. 1 anndf a side drop bus channel n vt/tu new data flag indication detected (unlatched): a 1 indicates that a new data flag (1001 or 0001/1101/1011/1000) has been detected in the v1 pointer byte for the vt/tu selected (i.e., bits 1-4 in the v1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). 0ansize a side drop bus channel n vt/tu incorrect pointer size detected (unlatched): a 1 indicates that the receive size indicator in the pointer (bits 5 and 6 in the v1 pointer byte) is not 11 (ds1) or 10 (e1) for the vt/tu selected. the detection and recovery time is immediate. address bit symbol description
temx8 txc-04218 - 188 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+112 7-2 not used: 1 anj2tim a side drop bus channel n j2 trail trace mismatch (unlatched) alarm: enabled when control bit arnj2ns1 and arnj2s0 are equal to 01. a 1 indication occurs when the alignment of the 16-byte j2 trace identifier label (message) has not been established. 0 anj2lol a side drop bus channel n j2 loss of lock (unlatched) alarm: enabled when control bit arnj2ns1 and arnj2s0 are equal to 01. a 1 indicates that the stable 16-byte message did not match for three mes- sage time. recovery occurs when the j2 state machine loses lock and then acquires lock with a 16-byte stable j2 message that matches the j2 comparison message written by the microprocessor three consecutive times. address bit symbol description
temx8 txc-04218 - 189 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+113 7 antclm a side drop bus channel n tandem connection loss of multiframe (unlatched) alarm: a 1 indicates that two or more consecutive errored multiframes have been detected in bits 7 and 8 in the n2 byte. recovery occurs when one consecutive non-errored multiframes (1111 1111 1111 1110) are detected. 6antcll a side drop bus channel n tandem connection trail trace mes- sage loss of lock (unlatched) alarm: a 1 indicates that the stable 16-byte message did not match for three message times. recovery occurs when the n2 state machine loses lock and then acquires lock with a 16-byte stable n2 message that matches the n2 comparison mes- sage written by the microprocessor three consecutive times. 5antctm a side drop bus channel n bus tandem connection trail trace message mismatch (unlatched) alarm: a 1 indicates that the stable tandem connection 16-byte message did not match for one message time. recovery occurs when the n2 byte tc message state machine loses lock and then acquires lock with a 16-byte stable n2 byte message that matches the n2 byte comparison message written by the micropro- cessor. 4antcais a side drop bus channel n tandem connection ais (unlatched) alarm: a 1 indicates that bit 4 in the n2 byte is equal to 1 for five or more consecutive frames. recovery occurs when bit 4 is a 0 for five or more consecutive frames. 3 antcuq a side drop bus channel n tandem connection unequipped (unlatched) alarm: a 1 indicates that bit 3 through 8 in the n2 byte is equal to 0 for 5 or more consecutive frames. recovery occurs when bits 3 through 8 are not all equal to 0 for 5 or more consecutive frames. 2 antcrdi a side drop bus channel n tandem connection rdi (unlatched) alarm: a 1 indicates that in the n2 byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. recovery occurs when bit 8 is a 0 for five or more consecutive frames. 1 antcodi a side drop bus channel n tandem connection odi (unlatched) alarm: a 1 indicates that in the n2 byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. recovery occurs when bit 7 is a 0 for five or more consecutive frames. 0 not used: address bit symbol description
temx8 txc-04218 - 190 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+114 7 not used: 6 lanvcais a side drop bus channel n vc ais latched alarm indication: this bit position latches for a a side vc ais alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 5 lanuneq a side drop bus channel n unequipped latched alarm indication: this bit position latches for a a side unequipped alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 4 lanrdic a side drop bus channel n remote connectivity defect latched alarm indication: this bit position latches for a a side remote connec- tivity defect alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3lanrdip a side drop bus channel n remote payload defect latched alarm indication: this bit position latches for a a side remote payload defect alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2lanrdis a side drop bus channel n remote server defect indication or sin- gle bit rdi latched alarm indication: this bit position latches for a a side remote server defect alarm or a single bit rdi alarm. this bit is set on either a positive transition, negative transition or positive and nega- tive alarm transition. this bit is cleared by writing a 0 into this bit location. 1 lansler a side drop bus channel n signal label mismatched latched alarm indication: this bit position latches for a a side signal label mis- match alarm indication. this bit is set on either a positive transition, neg- ative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0lanrfi a side drop bus channel n remote failure latched alarm indica- tion: this bit position latches for a a side remote failure indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 191 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+115 7-5 not used: 4 lanrffe a side drop bus channel n latched desynchronizer fifo error indication: this bit position latches for a a side desynchronizer fifo error indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3 lanais a side drop bus channel n vt/tu ais latched alarm indication: this bit position latches for a a side vt/tu ais alarm indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2lanlop a side drop bus channel n vt/tu loss of pointer latched alarm indication: this bit position latches for a a side vt/tu lop alarm indi- cation. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 1lanndf a side drop bus channel n vt/tu new data flag indication latched indication: this bit position latches for a a side vt/tu ndf indication. this bit is set on either a positive transition, negative transi- tion or positive and negative alarm transition. this bit is cleared on a read cycle. 0 lansize a side drop bus channel n vt/tu incorrect pointer size latched indication: this bit position latches for a a side vt/tu incorrect pointer indication. this bit is set on either a positive transition, negative transi- tion or positive and negative alarm transition. this bit is cleared on a read cycle. x+116 7-2 not used: 1lanj2tim a side drop bus channel n j2 trail trace mismatch latched alarm indication: this bit position latches for a a side j2 mismatch alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0 lanj2lol a side drop bus channel n j2 loss of lock latched alarm indica- tion: this bit position latches for a a side j2 loss of lock alarm. this bit is set on either a positive transition, negative transition or positive and neg- ative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 192 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+117 7 lantclm a side drop bus channel n tandem connection loss of multiframe latched alarm indication: this bit position latches for a a side tc loss of multiframe alarm. this bit is set on either a positive transition, nega- tive transition or positive and negative alarm transition. this bit is cleared on a read cycle. 6lantcll a side drop bus channel n tandem connection trail trace mes- sage loss of lock latched alarm indication: this bit position latches for a a side tc loss of lock alarm. this bit is set on either a positive tran- sition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 5 lantctm a side drop bus channel n bus tandem connection trail trace message mismatch latched alarm: this bit position latches for a a side tc mismatch alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 4 lantcais a side drop bus channel n tandem connection ais latched alarm indication: this bit position latches for a a side tc ais alarm indication. this bit is set on either a positive transition, negative transition or posi- tive and negative alarm transition. this bit is cleared on a read cycle. 3 lantcuq a side drop bus channel n tandem connection unequipped latched alarm indication: this bit position latches for a a side tc unequipped alarm indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2 lantcrdi a side drop bus channel n tandem connection rdi latched alarm indication: this bit position latches for a a side tc rdi alarm indication. this bit is set on either a positive transition, negative transition or posi- tive and negative alarm transition. this bit is cleared on a read cycle. 1lantcodi a side drop bus channel n tandem connection odi latched alarm indication: this bit position latches for a a side tc odi alarm indica- tion. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0 not used: address bit symbol description
temx8 txc-04218 - 193 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+118 7 not used: 6 panvcais a side drop bus channel n vc ais one second alarm indication: this bit position is set when the a side vc ais alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 5 panuneq a side drop bus channel n unequipped one second alarm indica- tion: this bit position is set when the a side unequipped alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 4 panrdic a side drop bus channel n remote connectivity defect one sec- ond alarm indication: this bit position is set when the a side remote connectivity defect alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an inter- rupt. 3 panrdip a side drop bus channel n remote payload defect one second alarm indication: this bit position is set when the a side remote pay- load defect alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2 panrdis a side drop bus channel n remote server defect indication or sin- gle bit rdi one sec ond alarm indication: this bit position is set when the a side remote server defect alarm or single bit rdi indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1 pansler a side drop bus channel n signal label mismatch one second alarm indication: this bit position is set when the a side signal label mismatch alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0panrfi a side drop bus channel n remote failure one second alarm indi- cation: this bit position is set when the a side remote failure indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 194 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+119 7-5 not used: 4 panrffe a side drop bus channel n desynchronizer one second fifo error indication: this bit position is set when the a side desynchronizer fifo error indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3 panais a side drop bus channel n vt/tu ais one second alarm indica- tion: this bit position is set when the a side vt/tu ais alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2 panlop a side drop bus channel n vt/tu loss of pointer one second alarm indication: this bit position is set when the a side vt/tu lop alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1 panndf a side drop bus channel n vt/tu new data flag indication one second indication: this bit position is set when the a side vt/tu ndf indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0pansize a side drop bus channel n vt/tu incorrect pointer size one sec- ond indication: this bit position is set when the a side vt/tu incorrect size indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. x+11a 7-2 not used: 1panj2tim a side drop bus channel n j2 trail trace mismatch one second alarm indication: this bit position is set when the a side j2 mismatch alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0panj2lol a side drop bus channel n j2 loss of lock one second alarm indication: this bit position is set when the a side j2 loss of lock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 195 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+11b 7 pantclm a side drop bus channel n tandem connection loss of multiframe one second alarm indication: this bit position is set when the a side tc loss of multiframe alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an inter- rupt. 6pantcll a side drop bus channel n tandem connection trail trace mes- sage loss of lock one second alarm indication: this bit position is set when the a side tc loss of lock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 5 pantctm a side drop bus channel n bus tandem connection trail trace message mismatch one second alarm: this bit position is set when the a side tc mismatch alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 4 pantcais a side drop bus channel n tandem connection ais one second alarm indication: this bit position is set when the a side tc ais alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3pantcuq a side drop bus channel n tandem connection unequipped one second alarm indication: this bit position is set when the a side tc unequipped alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2 pantcrdi a side drop bus channel n tandem connection rdi one second alarm indication: this bit position is set when the a side tc rdi alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1pantcodi a side drop bus channel n tandem connection odi one second alarm indication: this bit position is set when the a side tc odi alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0 not used: address bit symbol description
temx8 txc-04218 - 196 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+11c 7 not used: 6 fanvcais a side drop bus channel n vc ais persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the a side bip-2 error indication is active, but did not become active in the previous one second interval. 5 fanuneq a side drop bus channel n unequipped persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the a side unequipped alarm indication is active, but did not become active in the previous one second interval. 4 fanrdic a side drop bus channel n remote connectivity defect persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the a side remote connectivity defect alarm indication is active, but did not become active in the previous one sec- ond interval. 3fanrdip a side drop bus channel n remote payload defect persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the a side remote payload defect alarm indication is active, but did not become active in the previous one second interval. 2fanrdis a side drop bus channel n remote server defect indication or sin- gle bit rdi persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the a side remote server defect or single bit rdi alarm indication is active, but did not become active in the previous one second interval. 1 fansler a side drop bus channel n signal label mismatch persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the a side signal label mismatch alarm indication is active, but did not become active in the previous one second interval. 0fanrfi a side drop bus channel n remote failure persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the a side remote failure indication is active, but did not become active in the previous one second interval. address bit symbol description
temx8 txc-04218 - 197 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+11d 7-5 not used: 4 fanrffe a side drop bus channel n desynchronizer persistent one second fifo error indication: this bit position is set to 1 for the one-second interval, when the a side desynchronizer fifo error indication is active, but did not become active in the previous one second interval. 3 fanais a side drop bus channel n vt/tu ais persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the a side vt/tu ais alarm indication is active, but did not become active in the previous one second interval. 2fanlop a side drop bus channel n vt/tu loss of pointer persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the a side vt/tu lop alarm indication is active, but did not become active in the previous one second interval. 1fanndf a side drop bus channel n vt/tu new data flag indication persis- tent one second indication: this bit position is set to 1 for the one-second interval, when the a side vt/tu ndf indication is active, but did not become active in the previous one second interval. 0 fansize a side drop bus channel n vt/tu in correct pointer size persistent one second indication: this bit position is set to 1 for the one-second interval, when the a side vt/tu incorrect size indication is active, but did not become active in the previous one second interval. x+11e 7-2 not used: 1fanj2tim a side drop bus channel n j2 trail trace mismatch persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the a side j2 mismatch alarm indication is active, but did not become active in the previous one second interval. 0 fanj2lol a side drop bus channel n j2 loss of lock persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the a side j2 loss of lock alarm indication is active, but did not become active in the previous one second interval. x+11f 7 fantclm a side drop bus channel n tandem connection loss of multiframe persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the a side tc loss of multiframe alarm indication is active, but did not become active in the previous one sec- ond interval. 6fantcll a side drop bus channel n tandem connection trail trace mes- sage loss of lock persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the a side tc loss of lock alarm indication is active, but did not become active in the previ- ous one second interval. 5 fantctm a side drop bus channel n bus tandem connection trail trace message mismatch persistent one second alarm: this bit position is set to 1 for the one-second interval, when the a side tc mismatch alarm indication is active, but did not become active in the previous one sec- ond interval. address bit symbol description
temx8 txc-04218 - 198 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side drop counter descriptions (n = 1 to 8) x+11f (cont.) 4 fantcais a side drop bus channel n tandem connection ais persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the a side tc ais alarm indication is active, but did not become active in the previous one second interval. 3 fantcuq a side drop bus channel n tandem connection unequipped per- sistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the a side tc unequipped alarm indica- tion is active, but did not become active in the previous one second inter- val. 2 fantcrdi a side drop bus channel n tandem connection rdi persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the a side tc rdi alarm indication is active, but did not become active in the previous one second interval. 1fantcodi a side drop bus channel n tandem connection odi persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the a side odi alarm indication is active, but did not become active in the previous one second interval. 0 not used: address bit symbol description x+120 7-0 anpj counter a side drop bus channel n positive pointer justification counter: an eight bit counter that increments on a positive pointer movement for the vt/tu selected. x+121 7-0 annj counter a side drop bus channel n negative pointer justification counter: an eight bit counter that increments on a negative pointer movement for the vt/tu selected. x+122 7-0 anrei counter a side drop bus channel n rei counter: an 8-bit counter which counts the number of rei errors detected in bit 3 in v5 byte for the vt/tu selected. x+123 7-0 anbip2 counter a side drop bus channel n bip-2 counter: an 8-bit counter which counts the number of bip-2 errors detected for the vt/tu selected when control bit block is set to 0. a maximum of two errors can occur each frame. when the block control bit is set to 1, one or two errors is counted as a single block error. x+124 7-0 antc oei error counter a side drop bus channel n tandem connection oei counter: an 8-bit counter which counts the number of oei errors detected in bit 6 in the n2 byte for the tu/vt selected when the tandem connection feature is enabled. x+125 7-0 antc rei error counter a side drop bus channel n tandem connection rei counter: an 8-bit counter which counts the number of rei errors detected in bit 5 in the n2 byte for the vt/tu selected when the tandem connection feature is enabled. address bit symbol description
temx8 txc-04218 - 199 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+126 7-0 antc bip-2 error counter a side drop bus channel n tandem connection bip-2 counter: an 8-bit counter which counts the number of tc bip-2 errors detected for the vt/tu selected when control bit block is set to 0. a maximum of two errors can occur each frame. when the block control bit is set to 1, one or two errors is counted as a single block error. x+127 7-0 anpj previous 1 second counter (7-0) a side drop bus channel n previous one second positive pointer justification counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the previous one second interval. this location is updated from the a side positive justification counter at one second intervals. x+128 7-0 anpj previous 1 second counter (15-8) a side drop bus channel n previous one second positive pointer justification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the previous one second interval. this location is updated from the a side positive justification counter at one second intervals. x+129 7-0 annj previous 1 second counter (7-0) a side drop bus channel n previous one second negative pointer justification counter- low order byte: this counter holds the lower 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the previous one second interval. this location is updated from the a side current one second negative justification counter at one second intervals. x+12a 7-0 annj previous 1 second counter (15-8) a side drop bus channel n previous one second negative pointer justification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the previous one second interval. this location is updated from the a side current one second negative justification counter at one second intervals. x+12b 7-0 anrei previous 1 second counter (7-0) a side drop bus channel n previous one second rei counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for rei counts that occurred in the previous one second interval. this location is updated from the a side current one second rei counter at one second intervals. x+12c 7-0 anrei previous 1 second counter (15-8) a side drop bus channel n previous one second rei counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for rei counts that occurred in the previous one second interval. this location is updated from the a side current one second rei counter at one second intervals. x+12d 7-0 anbip2 previous 1 second counter (7-0) a side drop bus channel n previous one second bip-2 counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for bip-2 counts that occurred in the previous one second interval. this location is updated from the a side current one second bip-2 counter at one second intervals. x+12e 7-0 anbip2 previous 1 second counter (15-8) a side drop bus channel n previous one second bip-2 counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for bip-2 counts that occurred in the previous one second interval. this loca- tion is updated from the a side current one second bip-2 counter at one second intervals. address bit symbol description
temx8 txc-04218 - 200 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+135 7-0 anpj current 1 second counter (7-0) a side drop bus channel n current one second positive pointer jus- tification counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the current one second interval. this location is updated from the a side posi- tive justification counter at one second intervals. x+136 7-0 anpj current 1 second counter (15-8) a side drop bus channel n current one second positive pointer jus- tification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the current one second interval. this location is updated from the a side positive justification counter at one second intervals. x+137 7-0 annj current 1 second counter (7-0) a side drop bus channel n current one second negative pointer jus- tification counter- low order byte: this counter holds the lower 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the current one second interval. this location is updated from the a side current one second negative justification counter at one second intervals. x+138 7-0 annj current 1 second counter (15-8) a side drop bus channel n current one second negative pointer jus- tification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the current one second interval. this location is updated from the a side current one second negative justification counter at one second intervals. x+139 7-0 anrei current 1 second counter (7-0) a side drop bus channel n current one second rei counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for rei counts that occurred in the current one second interval. this location is updated from the a side current one second rei counter at one second intervals. x+13a 7-0 anrei current 1 second counter (15-8) a side drop bus channel n current one second rei counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for rei counts that occurred in the current one second interval. this location is updated from the a side current one second rei counter at one second intervals. x+13b 7-0 anbip2 current 1 second counter (7-0) a side drop bus channel n current one second bip-2 counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for bip-2 counts that occurred in the current one second interval. this location is updated from the a side current one second bip-2 counter at one second intervals. x+13c 7-0 anbip2 current 1 second counter (15-8) a side drop bus channel n current one second bip-2 counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for bip-2 counts that occurred in the current one second interval. this location is updated from the a side current one second bip-2 counter at one second intervals. address bit symbol description
temx8 txc-04218 - 201 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - a side drop bus overhead byte register descriptions (n = 1 to 8) address bit symbol description x+143 to x+182 7-0 a side drop bus j2 and n2 message segments a side drop bus channel n j2 and n2 byte message segments: the following locations store the a side drop bus 64-byte j2 message when control bit anj2s1 is a 1, and 16-byte j2 and n2 drop and microprocessor written comparison messages when control bit arnj2s1 is a 0. the follow- ing list the location of the drop message segments and the microprocessor written segments. location message segment 143h - 182h a side drop bus - j2 byte 64 byte message. or 143h - 152h a side drop bus - j2 byte 16 byte message 153h - 162h a side drop bus - n2 byte 16 byte message 163h - 172h a side microprocessor - j2 byte 16 byte message 173h - 182h a side microprocessor - n2 byte 16 byte message x+183 7-0 a side drop bus v1 byte a side drop bus channel n v1 byte: this register is updated every 500 microseconds. this location stores the a side drop bus v1 byte pointer byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v1 byte. x+184 7-0 a side drop bus v2 byte a side drop bus channel n v2 byte: this register is updated every 500 microseconds. this location stores the a side drop bus v2 byte pointer byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v2 byte. x+185 7-0 a side drop bus v4 byte a side drop bus channel n v4 byte: this register is updated every 500 microseconds. this location stores the a side drop bus v4 byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v4 byte. x+186 7-0 a side drop bus v5 byte a side drop bus channel n v5 overhead byte: this register is updated every 500 microseconds. this location stores the a side drop bus v5 over- head byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v5 byte. x+187 7-0 a side drop bus j2 byte a side drop bus channel n j2 overhead byte: this register is updated every 500 microseconds. this location stores the a side drop bus j2 over- head j2 byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v5 byte. x+188 7-0 a side drop bus n2 byte a side drop bus channel n n2 overhead byte: this register is updated every 500 microseconds. this location stores the a side drop bus n2 over- head byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the n2 byte. x+189 7-0 a side drop bus k4 byte a side drop bus channel n k4 overhead byte: this register is updated every 500 microseconds. this location stores the a side drop bus k4 over- head byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the k4 byte.
temx8 txc-04218 - 202 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop bus alarm mask bits (n = 1 to 8) x+18a 7-0 a side drop bus o-bits a side drop bus channel n o-bits: the two nibbles (bits 7-4 and 3-0) in this register correspond to the two sets of four overhead communication bits for the vt/tu selected. bit 7 corresponds to bit 3 in the first justification control byte, while bit 0 corresponds to bit 6 in the second justification con- trol byte. the two nibbles written into this register location will be from the same frame, updated every 500 microseconds. address bit symbol description x+083 7 not used: 6mbnvais b side drop bus channel n vc ais alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side drop bus vc ais latched bit alarm indication for channel n. 5mbnuqe b side drop bus channel n unequipped indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side unequipped latched bit alarm indication for channel n. 4 mbnrdic b side drop bus channel n remote connectivity defect indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side remote connectivity defect latched bit alarm indication for channel n. 3 mbnrdip b side drop bus channel n remote payload defect indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side remote payload defect latched bit alarm indication for channel n. 2 mbnrdis b side drop bus channel n remote server defect indication or sin- gle bit rdi alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side remote server defect or single bit rdi latched bit alarm indication for channel n. 1 mbnsler b side drop bus channel n signal label mismatch alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side signal label alarm latched bit alarm indication for channel n. 0mbnrfi b side drop bus channel n remote failure indication alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side remote failure indication alarm for channel n. x+084 7-5 not used: 4mbnrfe b side drop bus channel n fifo error indication mask bit: setting this bit to 1 a 1 enables the hardware interrupt for a b side fifo error indication latched bit alarm indication for channel n. 3 mbnais b side drop bus channel n vt/tu ais alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side vt/tu ais alarm latched bit alarm indication for channel n. address bit symbol description
temx8 txc-04218 - 203 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+084 (cont.) 2 mbnlop b side drop bus channel n vt/tu loss of pointer alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side loss of pointer alarm latched bit alarm indication for channel n. 1 mbnndf b side drop bus channel n vt/tu new data flag indication indica- tion mask bit: setting this bit to 1 enables the hardware interrupt for a b side ndf latched bit indication for channel n. 0mbnsize b side drop bus channel n vt/tu in correct pointer size indication mask bit: setting this bit to 1 enables the hardware interrupt for a b side vt/tu incorrect pointer latched bit indication for channel n. x+085 7-2 not used: 1mbnj2tim b side drop bus channel n j2 loss of lock alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side j2 loss of lock alarm latched bit indication for channel n. 0mbnj2lol b side drop bus channel n j2 trail trace mismatch alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side j2 mismatch alarm latched bit indication for channel n. x+086 7 mbntclm b side drop bus channel n tandem connection loss of multiframe alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side tc loss of multiframe alarm latched bit indication for channel n. 6mbntcll b side drop bus channel n tandem connection loss of lock alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side tc loss of lock alarm latched bit indication for channel n. 5 mbntctm b side drop bus channel n tandem connection trail trace mes- sage alarm mask bit: setting this bit to 1 enables the hardware inter- rupt for a b side tc mismatch alarm latched bit indication for channel n. 4 mbntcais b side drop bus channel n tandem connection ais alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side tc ais alarm latched bit indication for channel n. 3mbntcuq b side drop bus channel n tandem connection unequipped alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side tc unequipped alarm latched bit indication for channel n. 2 mbntcrdi b side drop bus port n tandem connection rdi alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side tc rdi alarm latched bit indication for channel n. 1mbntcodi b side drop bus channel n tandem connection odi alarm mask bit: setting this bit to 1 enables the hardware interrupt for a b side tc odi alarm latched bit indication for channel n. 0 not used: address bit symbol description
temx8 txc-04218 - 204 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop status register descriptions (n = 1 to 8) the following descriptions pertain to the status registers assigned to channel n for the b side drop bus. the status registers provide four readable bit positions per alarm. the alarm status are provided as unlatched alarm indications, latched alarm indications, one second indications, and previous one second indications. the latched bit position is set on positive, negative, or both positive and negative transitions of the alarm. b latched alarm is cleared on a microprocessor read cycle of its address. address bit symbol description x+190 7 not used: 6bnvcais b side drop bus channel n vc ais indication (unlatched) detected: a vc ais state is defined as a signal label equal to 111 (bits 5-7 in v5 byte). a 1 indicates that an vc ais has been detected in the v5 signal label for the tu/vt selected for five or more consecutive received vc ais signal labels. recovery occurs when five or more con- secutive signal labels are received not equal to 111. 5bnuneq b side drop bus channel n unequipped indication (unlatched) detected: a 1 indicates that an unequipped status has been detected in the v5 signal label (bits 5-7 in v5 byte are equal to 000) for the tu/vt selected for five or more consecutive received unequipped signal labels. recovery occurs when five or more consecutive signal labels are received not equal to 000. 4 bnrdic b side drop bus channel n remote connectivity defect indication (unlatched) detected: a 1 indicates that a remote connectivity defect alarm has been detected. the number of consecutive events used for detection and recovery is determined by control bit v5al10. 3bnrdip b side drop bus channel n remote payload defect indication (unlatched) detected: a 1 indicates that a remote payload defect alarm has been detected. the number of consecutive events used for detec- tion and recovery is determined by control bit v5al10. 2bnrdis b side drop bus channel n remote server defect indication or sin- gle bit rdi (unlatched) detected: a 1 indicates that a remote server defect alarm or a single bit rdi state has been detected. the number of consecutive events used for detection and recovery is determined by control bit v5al10. 1 bnsler b side drop bus channel n signal label mismatch detected (unlatched): a 1 indicates that the dropped signal label (bits 5-7 in v5 byte) for the vt/tu selected does not match the microprocessor-written signal label for five or more consecutive events. recovery occurs when five or more consecutive correct signal labels are detected. 0bnrfi b side drop bus channel n remote failure indication detected (unlatched): a 1 indicates that bit 4 in the v5 byte is equal to 1 for the vt/tu selected. the detection and recovery time is five consecutive multiframes.
temx8 txc-04218 - 205 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+191 7-5 not used: 4 bnrffe b side drop bus channel n fifo error (unlatched): a 1 indicates that the receive fifo in the desynchronizer for channel n has overflowed or underflowed for the vt/tu selected. the fifo is reset automatically. line ais will be sent for two multiframes when enabled. 3bnais b side drop bus channel n vt/tu ais detected (unlatched): a 1 indicates that a ais state has been detected in the v1/v2 pointer bytes for the vt/tu selected. 2bnlop b side drop bus channel n vt/tu loss of pointer detected (unlatched): a 1 indicates that a loss of pointer (lop) has been detected in the v1/v2 pointer bytes for the vt/tu selected. 1 bnndf b side drop bus channel n vt/tu new data flag indication detected (unlatched): a 1 indicates that a new data flag (1001 or 0001/1101/1011/1000) has been detected in the v1 pointer byte for the vt/tu selected (i.e., bits 1-4 in the v1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). 0bnsize b side drop bus channel n vt/tu incorrect pointer size detected (unlatched): a 1 indicates that the receive size indicator in the pointer (bits 5 and 6 in the v1 pointer byte) is not 11 (ds1) or 10 (e1) for the vt/tu selected. the detection and recovery time is immediate. x+192 7-2 not used: 1 bnj2tim b side drop bus channel n j2 trail trace mismatch (unlatched) alarm: enabled when control bit brnj2s1 and brnj2s0 are equal to 01. a 1 indication occurs when the alignment of the 16-byte j2 trace identifier label (message) has not been established. 0 bnj2lol b side drop bus channel n j2 loss of lock (unlatched) alarm: enabled when control bit brnj2s1 and brnj2s0 are equal to 01. a 1 indicates that the stable 16-byte message did not match for three mes- sage time. recovery occurs when the j2 state machine loses lock and then acquires lock with a 16-byte stable j2 message that matches the j2 comparison message written by the microprocessor for three consecu- tive times. address bit symbol description
temx8 txc-04218 - 206 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+193 7 bntclm b side drop bus channel n tandem connection loss of multiframe (unlatched) alarm: a 1 indicates that two or more consecutive errored multiframes have been detected in bits 7 and 8 in the n2 byte. recovery occurs when one consecutive non-errored multiframes (1111 1111 1111 1110) are detected. 6bntcll b side drop bus channel n tandem connection trail trace mes- sage loss of lock (unlatched) alarm: a 1 indicates that the stable 16 -byte message did not match for three message times. recovery occurs when the n2 state machine loses lock and then acquires lock with a 16-byte stable n2 message that matches the n2 comparison message written by the microprocessor for 3 consecutive times. 5bntctm b side drop bus channel n bus tandem connection trail trace message mismatch (unlatched) alarm: a 1 indicates that the stable tandem connection 16-byte message did not match for one message time. recovery occurs when the n2 byte tc message state machine loses lock and then acquires lock with a 16-byte stable n2 byte message that matches the n2 byte comparison message written by the micropro- cessor. 4bntcais b side drop bus channel n tandem connection ais (unlatched) alarm: a 1 indicates that bit 4 in the n2 byte is equal to 1 for five or more consecutive frames. recovery occurs when bit 4 is a 0 for five or more consecutive frames. 3 bntcuq b side drop bus channel n tandem connection unequipped (unlatched) alarm: a 1 indicates that bit 3 through 8 in the n2 byte is equal to 0 for 5 or more consecutive frames. recovery occurs when bits 3 through 8 are not all equal to 0 for 5 or more consecutive frames. 2 bntcrdi b side drop bus channel n tandem connection rdi (unlatched) alarm: a 1 indicates that in the n2 byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. recovery occurs when bit 8 is a 0 for five or more consecutive frames. 1 bntcodi b side drop bus channel n tandem connection odi (unlatched) alarm: a 1 indicates that in the n2 byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. recovery occurs when bit 7 is a 0 for five or more consecutive frames. 0 not used: address bit symbol description
temx8 txc-04218 - 207 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+194 7 not used: 6 lbnvcais b side drop bus channel n vc ais latched alarm indication: this bit position latches for a b side vc ais alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 5 lbnuneq b side drop bus channel n unequipped latched alarm indication: this bit position latches for a b side unequipped alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 4 lbnrdic b side drop bus channel n remote connectivity defect latched alarm indication: this bit position latches for a b side remote connec- tivity defect alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3lbnrdip b side drop bus channel n remote payload defect latched alarm indication: this bit position latches for a b side remote payload defect alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2lbnrdis b side drop bus channel n remote server defect indication or sin- gle bit rdi latched alarm indication: this bit position latches for a b side remote server defect alarm or a single bit rdi alarm. this bit is set on either a positive transition, negative transition or positive and nega- tive alarm transition. this bit is cleared on a read cycle. 1 lbnsler b side drop bus channel n signal label mismatched latched alarm indication: this bit position latches for a b side signal label mis- match alarm indication. this bit is set on either a positive transition, neg- ative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0 lbnrfi b side drop bus channel n remote failure latched alarm indica- tion: this bit position latches for a b side remote failure indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 208 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+195 7-5 not used: 4 lbnrffe b side drop bus channel n latched desynchronizer fifo error indication: this bit position latches for a b side desynchronizer fifo error indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 3 lbnais b side drop bus channel n vt/tu ais latched alarm indication: this bit position latches for a b side vt/tu ais alarm indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2lbnlop b side drop bus channel n vt/tu loss of pointer latched alarm indication: this bit position latches for a b side vt/tu lop alarm indi- cation. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 1lbnndf b side drop bus channel n vt/tu new data flag indication latched indication: this bit position latches for a b side vt/tu ndf indication. this bit is set on either a positive transition, negative transi- tion or positive and negative alarm transition. this bit is cleared on a read cycle. 0 lbnsize b side drop bus channel n vt/tu incorrect pointer size latched indication: this bit position latches for a b side vt/tu incorrect pointer indication. this bit is set on either a positive transition, negative transi- tion or positive and negative alarm transition. this bit is cleared on a read cycle. x+196 7-2 not used: 1lbnj2tim b side drop bus channel n j2 trail trace mismatch latched alarm indication: this bit position latches for a b side j2 mismatch alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0 lbnj2lol b side drop bus channel n j2 loss of lock latched alarm indica- tion: this bit position latches for a b side j2 loss of lock alarm. this bit is set on either a positive transition, negative transition or positive and neg- ative alarm transition. this bit is cleared on a read cycle. address bit symbol description
temx8 txc-04218 - 209 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+197 7 lbntclm b side drop bus channel n tandem connection loss of multiframe latched alarm indication: this bit position latches for a b side tc loss of multiframe alarm. this bit is set on either a positive transition, nega- tive transition or positive and negative alarm transition. this bit is cleared on a read cycle. 6lbntcll b side drop bus channel n tandem connection trail trace mes- sage loss of lock latched alarm indication: this bit position latches for a b side tc loss of lock alarm. this bit is set on either a positive tran- sition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 5 lbntctm b side drop bus channel n bus tandem connection trail trace message mismatch latched alarm: this bit position latches for a b side tc mismatch alarm. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 4 lbntcais b side drop bus channel n tandem connection ais latched alarm indication: this bit position latches for a b side tc ais alarm indication. this bit is set on either a positive transition, negative transition or posi- tive and negative alarm transition. this bit is cleared on a read cycle. 3 lbntcuq b side drop bus channel n tandem connection unequipped latched alarm indication: this bit position latches for a b side tc unequipped alarm indication. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 2 lbntcrdi b side drop bus channel n tandem connection rdi latched alarm indication: this bit position latches for a b side tc rdi alarm indication. this bit is set on either a positive transition, negative transition or posi- tive and negative alarm transition. this bit is cleared on a read cycle. 1lbntcodi b side drop bus channel n tandem connection odi latched alarm indication: this bit position latches for a b side tc odi alarm indica- tion. this bit is set on either a positive transition, negative transition or positive and negative alarm transition. this bit is cleared on a read cycle. 0 not used: address bit symbol description
temx8 txc-04218 - 210 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+198 7 not used: 6 pbnvcais b side drop bus channel n vc ais one second alarm indication: this bit position is set when the b side vc ais alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 5 pbnuneq b side drop bus channel n unequipped one second alarm indica- tion: this bit position is set when the b side unequipped alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 4 pbnrdic b side drop bus channel n remote connectivity defect one sec- ond alarm indication: this bit position is set when the b side remote connectivity defect alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an inter- rupt. 3 pbnrdip b side drop bus channel n remote payload defect one second alarm indication: this bit position is set when the b side remote pay- load defect alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2 pbnrdis b side drop bus channel n remote server defect indication or sin- gle bit rdi one sec ond alarm indication: this bit position is set when the b side remote server defect alarm or single bit rdi indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1 pbnsler b side drop bus channel n signal label mismatch one second alarm indication: this bit position is set when the b side signal label mismatch alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0pbnrfi b side drop bus channel n remote failure one second alarm indi- cation: this bit position is set when the b side remote failure indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 211 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+199 7-5 not used: 4 pbnrffe b side drop bus channel n desynchronizer one second fifo error indication: this bit position is set when the b side desynchronizer fifo error indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3pbnais b side drop bus channel n vt/tu ais one second alarm indica- tion: this bit position is set when the b side vt/tu ais alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2pbnlop b side drop bus channel n vt/tu loss of pointer one second alarm indication: this bit position is set when the b side vt/tu lop alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1 pbanndf b side drop bus channel n vt/tu new data flag indication one second indication: this bit position is set when the b side vt/tu ndf indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0 pbnsize b side drop bus channel n vt/tu incorrect pointer size one sec- ond indication: this bit position is set when the b side vt/tu incorrect size indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. x+19a 7-2 not used: 1 pbnj2tim b side drop bus channel n j2 trail trace mismatch one second alarm indication: this bit position is set when the b side j2 mismatch alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0 pbnj2lol b side drop bus channel n j2 loss of lock one second alarm indication: this bit position is set when the b side j2 loss of lock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. address bit symbol description
temx8 txc-04218 - 212 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+19b 7 pbntclm b side drop bus channel n tandem connection loss of multiframe one second alarm indication: this bit position is set when the b side tc loss of multiframe alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an inter- rupt. 6pbntcll b side drop bus channel n tandem connection trail trace mes- sage loss of lock one second alarm indication: this bit position is set when the b side tc loss of lock alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 5 pbntctm b side drop bus channel n bus tandem connection trail trace message mismatch one second alarm: this bit position is set when the b side tc mismatch alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 4 pbntcais b side drop bus channel n tandem connection ais one second alarm indication: this bit position is set when the b side tc ais alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 3pbntcuq b side drop bus channel n tandem connection unequipped one second alarm indication: this bit position is set when the b side tc unequipped alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 2 pbntcrdi b side drop bus channel n tandem connection rdi one second alarm indication: this bit position is set when the b side tc rdi alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 1pbntcodi b side drop bus channel n tandem connection odi one second alarm indication: this bit position is set when the b side tc odi alarm indication has changed state in the last one second interval or is 1 at the end of the interval. this bit is disabled if the one second pulse is not applied. this indication does not cause an interrupt. 0 not used: address bit symbol description
temx8 txc-04218 - 213 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+19c 7 not used: 6 fbnvcais b side drop bus channel n vc ais persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side bip-2 error indication is active, but did not become active in the previous one second interval. 5 fbnuneq b side drop bus channel n unequipped persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the b side unequipped alarm indication is active, but did not become active in the previous one second interval. 4fbnrdic b side drop bus channel n remote connectivity defect persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side remote connectivity defect alarm indication is active, but did not become active in the previous one sec- ond interval. 3 fbnrdip b side drop bus channel n remote payload defect persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the b side remote payload defect alarm indication is active, but did not become active in the previous one second interval. 2 fbnrdis b side drop bus channel n remote server defect indication or sin- gle bit rdi persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side remote server defect or single bit rdi alarm indication is active, but did not become active in the previous one second interval. 1 fbnsler b side drop bus channel n signal label mismatch persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the b side signal label mismatch alarm indication is active, but did not become active in the previous one second interval. 0fbnrfi b side drop bus channel n remote failure persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the b side remote failure indication is active, but did not become active in the previous one second interval. address bit symbol description
temx8 txc-04218 - 214 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+19d 7-5 not used: 4fbnrffe b side drop bus channel n desynchronizer persistent one second fifo error indication: this bit position is set to 1 for the one-second interval, when the b side desynchronizer fifo error indication is active, but did not become active in the previous one second interval. 3 fbnais b side drop bus channel n vt/tu ais persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the b side vt/tu ais alarm indication is active, but did not become active in the previous one second interval. 2 fbnlop b side drop bus channel n vt/tu loss of pointer persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the b side vt/tu lop alarm indication is active, but did not become active in the previous one second interval. 1 fbnndf b side drop bus channel n vt/tu new data flag indication persis- tent one second indication: this bit position is set to 1 for the one-second interval, when the b side vt/tu ndf indication is active, but did not become active in the previous one second interval. 0 fbnsize b side drop bus channel n vt/tu incorrect pointer size persistent one second indication: this bit position is set to 1 for the one-second interval, when the b side vt/tu incorrect size indication is active, but did not become active in the previous one second interval x+19e 7-2 not used: 1fbnj2tim b side drop bus channel n j2 trail trace mismatch persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the b side j2 mismatch alarm indication is active, but did not become active in the previous one second interval. 0fbnj2lol b side drop bus channel n j2 loss of lock persistent one second alarm indication: this bit position is set to 1 for the one-second inter- val, when the b side j2 loss of lock alarm indication is active, but did not become active in the previous one second interval. address bit symbol description
temx8 txc-04218 - 215 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop counter descriptions (n = 1 to 8) x+19f 7 fbntclm b side drop bus channel n tandem connection loss of multiframe persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side tc loss of multiframe alarm indication is active, but did not become active in the previous one sec- ond interval. 6fbntcll b side drop bus channel n tandem connection trail trace mes- sage loss of lock persistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side tc loss of lock alarm indication is active, but did not become active in the previ- ous one second interval. 5 fbntctm b side drop bus channel n bus tandem connection trail trace message mismatch persistent one second alarm: this bit position is set to 1 for the one-second interval, when the b side tc mismatch alarm indication is active, but did not become active in the previous one sec- ond interval. 4 fbntcais b side drop bus channel n tandem connection ais persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the b side tc ais alarm indication is active, but did not become active in the previous one second interval. 3 fbntcuq b side drop bus channel n tandem connection unequipped per- sistent one second alarm indication: this bit position is set to 1 for the one-second interval, when the b side tc unequipped alarm indica- tion is active, but did not become active in the previous one second inter- val. 2 fbntcrdi b side drop bus channel n tandem connection rdi persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the b side tc rdi alarm indication is active, but did not become active in the previous one second interval. 1fbntcodi b side drop bus channel n tandem connection odi persistent one second alarm indication: this bit position is set to 1 for the one-sec- ond interval, when the b side odi alarm indication is active, but did not become active in the previous one second interval. 0 not used: address bit symbol description x+1a0 7-0 bnpj counter b side drop bus channel n positive pointer justification counter: an eight bit counter that increments on a positive pointer movement for the vt/tu selected. x+1a1 7-0 bnnj counter b side drop bus channel n negative pointer justification counter: an eight bit counter that increments on a negative pointer movement for the vt/tu selected. x+1a2 7-0 bnrei counter b side drop bus channel n rei counter: an 8-bit counter which counts the number of rei errors detected in bit 3 in v5 byte for the vt/tu selected. address bit symbol description
temx8 txc-04218 - 216 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+1a3 7-0 bnbip2 counter b side drop bus channel n bip-2 counter: an 8-bit counter which counts the number of bip-2 errors detected for the vt/tu selected when control bit block is set to 0. a maximum of two errors can occur each frame. when the block control bit is set to 1, one or two errors is counted as a single block error. x+1a4 7-0 bntc oei error counter b side drop bus channel n tandem connection oei counter: an 8-bit counter which counts the number of oei errors detected in bit 6 in the n2 byte for the tu/vt selected when the tandem connection feature is enabled. x+1a5 7-0 bntc rei error counter b side drop bus channel n tandem connection rei counter: an 8-bit counter which counts the number of rei errors detected in bit 5 in the n2 byte for the vt/tu selected when the tandem connection feature is enabled. x+1a6 7-0 bntc bip-2 error counter b side drop bus channel n tandem connection bip-2 counter: an 8-bit counter which counts the number of tc bip-2 errors detected for the vt/tu selected when control bit block is set to 0. a maximum of two errors can occur each frame. when the block control bit is set to 1, one or two errors is counted as a single block error. x+1a7 7-0 bnpj previous 1 second counter (7-0) b side drop bus channel n previous one second positive pointer justification counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the previous one second interval. this location is updated from the b side positive justification counter at one second intervals. x+1a8 7-0 bnpj previous 1 second counter (15-8) b side drop bus channel n previous one second positive pointer justification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the previous one second interval. this location is updated from the b side positive justification counter at one second intervals. x+1a9 7-0 bnnj previous 1 second counter (7-0) b side drop bus channel n previous one second negative pointer justification counter- low order byte: this counter holds the lower 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the previous one second interval. this location is updated from the b side current one second negative justification counter at one second intervals. x+1aa 7-0 bnnj previous 1 second counter (15-8) b side drop bus channel n previous one second negative pointer justification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the previous one second interval. this location is updated from the b side current one second negative justification counter at one second intervals. x+1ab 7-0 bnrei previous 1 second counter (7-0) b side drop bus channel n previous one second rei counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for rei counts that occurred in the previous one second interval. this location is updated from the b side current one second rei counter at one second intervals. address bit symbol description
temx8 txc-04218 - 217 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+1ac 7-0 bnrei previous 1 second counter (15-8) b side drop bus channel n previous one second rei counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for rei counts that occurred in the previous one second interval. this location is updated from the b side current one second rei counter at one second intervals. x+1ad 7-0 bnbip2 previous 1 second counter (7-0) b side drop bus channel n previous one second bip-2 counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for bip-2 counts that occurred in the previous one second interval. this location is updated from the b side current one second bip-2 counter at one second intervals. x+1ae 7-0 bnbip2 previous 1 second counter (15-8) b side drop bus channel n previous one second bip-2 counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for bip-2 counts that occurred in the previous one second interval. this loca- tion is updated from the b side current one second bip-2 counter at one second intervals. x+1b5 7-0 bnpj current 1 second counter (7-0) b side drop bus channel n current one second positive pointer jus- tification counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the current one second interval. this location is updated from the b side posi- tive justification counter at one second intervals. x+1b6 7-0 bnpj current 1 second counter (15-8) b side drop bus channel n current one second positive pointer jus- tification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for positive pointer justification counts that occurred in the current one second interval. this location is updated from the b side positive justification counter at one second intervals. x+1b7 7-0 bnnj current 1 second counter (7-0) b side drop bus channel n current one second negative pointer jus- tification counter- low order byte: this counter holds the lower 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the current one second interval. this location is updated from the b side current one second negative justification counter at one second intervals. x+1b8 7-0 bnnj current 1 second counter (15-8) b side drop bus channel n current one second negative pointer jus- tification counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for negative pointer justification counts that occurred in the current one second interval. this location is updated from the b side current one second negative justification counter at one second intervals. x+1b9 7-0 bnrei current 1 second counter (7-0) b side drop bus channel n current one second rei counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for rei counts that occurred in the current one second interval. this location is updated from the b side current one second rei counter at one second intervals. x+1ba 7-0 bnrei current 1 second counter (15-8) b side drop bus channel n current one second rei counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for rei counts that occurred in the current one second interval. this location is updated from the b side current one second rei counter at one second intervals. address bit symbol description
temx8 txc-04218 - 218 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 channel n - b side drop bus overhead byte register descriptions (n = 1 to 8) x+1bb 7-0 bnbip2 current 1 second counter (7-0) b side drop bus channel n current one second bip-2 counter - low order byte: this counter holds the lower 8 bits of a 16 bit counter for bip-2 counts that occurred in the current one second interval. this location is updated from the b side current one second bip-2 counter at one second intervals. x+1bc 7-0 bnbip2 current 1 second counter (15-8) b side drop bus channel n current one second bip-2 counter - high order byte: this counter holds the higher 8 bits of a 16 bit counter for bip-2 counts that occurred in the current one second interval. this location is updated from the b side current one second bip-2 counter at one second intervals. address bit symbol description x+1c3 to x+202 7-0 b side drop bus j2 and n2 message segments b side drop bus channel n j2 and n2 byte message segments: the following locations store the b side drop bus 64-byte j2 message when control bit bnj2s1 is a 1, and 16-byte j2 and n2 drop and microprocessor written comparison messages when control bit bnj2s1 is a 0. the following list the location of the drop message segments and the microprocessor writ- ten segments. location message segment 1c3h - 202 b side drop bus - j2 byte 64 byte message. or 1c3h - 1d2h b side drop bus - j2 byte 16 byte message 1d3h - 1e2h b side drop bus - n2 byte 16 byte message 1e3h - 1f2h b side microprocessor - j2 byte 16 byte message 1f3h - 202h b side microprocessor - n2 byte 16 byte message x+203 7-0 b side drop bus v1 byte b side drop bus channel n v1 byte: this register is updated every 500 microseconds. this location stores the b side drop bus v1 byte pointer byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v1 byte. x+204 7-0 b side drop bus v2 byte b side drop bus channel n v2 byte: this register is updated every 500 microseconds. this location stores the b side drop bus v2 byte pointer byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v2 byte. x+205 7-0 b side drop bus v4 byte b side drop bus channel n v4 byte: this register is updated every 500 microseconds. this location stores the b side drop bus v4 byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v4 byte. x+206 7-0 b side drop bus v5 byte b side drop bus channel n v5 overhead byte: this register is updated every 500 microseconds. this location stores the b side drop bus v5 over- head byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v5 byte. x+207 7-0 b side drop bus j2 byte b side drop bus channel n j2 overhead byte: this register is updated every 500 microseconds. this location stores the b side drop bus j2 over- head j2 byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the v5 byte. address bit symbol description
temx8 txc-04218 - 219 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 x+208 7-0 b side drop bus n2 byte b side drop bus channel n n2 overhead byte: this register is updated every 500 microseconds. this location stores the b side drop bus n2 over- head byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the n2 byte. x+209 7-0 b side drop bus k4 byte b side drop bus channel n k4 overhead byte: this register is updated every 500 microseconds. this location stores the b side drop bus k4 over- head byte for the vt/tu selected. bit 7 in this register corresponds to bit 1 in the k4 byte. x+20a 7-0 b side drop bus o-bits b side drop bus channel n o-bits: the two nibbles (bits 7-4 and 3-0) in this register correspond to the two sets of four overhead communication bits for the vt/tu selected. bit 7 corresponds to bit 3 in the first justification control byte, while bit 0 corresponds to bit 6 in the second justification con- trol byte. the two nibbles written into this register location will be from the same frame, updated every 500 microseconds. address bit symbol description
temx8 txc-04218 - 220 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 package information the temx8 device is packaged in a 376-lead plastic ball grid array (pbga) package suitable for surface mount- ing, as illustrated in figure 43 . figure 43. temx8 txc-04218 376-lead plastic ball grid array package d d2 note 2 e1/4 d1/4 a2 (a3) a a1 transwitch txc-04218aiog e e2 a rpnm kjhgfedcb 1 2 3 4 5 6 7 8 9 11 12 13 14 15 b e -d1- bottom view t 16 l 17 18 19 20 21 22 u ab aa y w v 10 -e1- dimension (note 1) min max notes: 1. all dimensions are in millimeters. values shown are for reference only. 2. identification of the solder ball a1 corner is con- tained within this shaded zone. package corner may not be a 90 angle. 3. size of array: 22 x 22, jedec code mo-151. a a1 a2 2.02 0.40 1.12 2.44 0.60 1.22 a3 (ref.) 0.56 b0.500.70 d23.00 d1 (nom) 21.00 d2 19.45 20.20 e23.00 e1 (nom) 21.00 e2 19.45 20.20 e (ref.) 1.00
temx8 txc-04218 - 221 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 ordering information part number: txc-04218aiog 376-lead plastic ball grid array package (pbga) related products txc-03103, qt1f- plus device (quad t1 framer- plus ). a 4-channel framer for voice and data applications. this device handles all logical interfacing functionality to a t1 line. this device requires a 5.0 volt supply. the new txc-03103c device provides the same functionality but can operate either from a 5 volt supply or from a 3.3 volt supply at lower power dissipation. txc-03108, t1fx8 device (8-channel t1 framer). an eight-channel ds1 (1544 kbit/s) framer for voice and data communications applications. this device handles all logical interfacing functionality to a t1 line and operates from a power supply of 3.3 volts. txc-03109, e1fx8 device (8-channel e1 framer). the e1fx8 is an eight-channel e1 (2048 kbit/s) framer designed with extended features for voice and data communications applications. ami and hdb3 line codes are supported with full alarm detection and generation per itu-t g.703, g.775 and i.431. txc-03114, qe1f- plus device (quad e1 framer- plus ). the qe1f- plus is a four-channel e1 (2048 kbit/s) framer designed for voice and data communications applications. a dual unipolar or nrz line interface is supported with full alarm detection and generation per itu-t g.703 and operates from a power supply of 3.3 or 5 volts. txc-04222, temx28 device (21/28 channel dual bus high density mapper). the temx28 device is designed for add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. up to 28 e1, ds1, or vt/tu payloads are mapped to and from vt1.5/tu-11s and vt2/tu-12s carried in an stm-1 vc-4 or sts-3 format. txc-06103, phast-3n device (sonet/sdh stm-1, sts-3 or sts-3c overhead terminator). the phast-3n provides a telecom bus interface for downstream devices and operates from a power supply of 3.3 volts.
temx8 txc-04218 - 222 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 reference documents itu-t, bellcore tr-253 ansi t1.105
temx8 txc-04218 - 223 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 25 west 43 rd street fax: (212) 398-0023 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 404 balboa street tel: (415) 561-6275 san francisco, ca 94118 fax: (415) 561-6120 web: www.atmforum.com atm forum europe office kingsland house - 5 th floor tel: 20 7837 7882 361-373 city road fax: 20 7417 7500 london ec1 1pq, england atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt (see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (303) 397-7956 (outside u.s.a.) 15 inverness way east fax: (303) 397-2740 englewood, co 80112 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 00 fax: 4 93 65 47 16 650 route des lucioles web: www.etsi.org 06921 sophia-antipolis cedex, france
temx8 txc-04218 - 224 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (903) 769-3818 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5852 fax: 22 730 5853 telecommunication standardization sector web: www.itu.int place des nations, ch 1211 geneve 20, switzerland jedec (international): joint electron device engineering council tel: (703) 907-7559 2500 wilson boulevard fax: (703) 907-7583 arlington, va 22201-3834 web: www.jedec.org mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 fax: (215) 697-1462 building 4 / section d web: www.dodssp.daps.mil 700 robbins avenue philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 5440 sw westgate dr., #217 tel: (503) 291-2569 (outside u.s.a.) portland, or 97221 fax: (503) 297-1090 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-2673 (within u.s.a.) attention - customer service tel: (732) 699-2000 (outside u.s.a.) 8 corporate place rm 3a184 fax: (732) 336-2559 piscataway, nj 08854-4157 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunication technology committee tel: 3 3432 1551 fax: 3 3432 1553 hamamatsu-cho suzuki building web: www.ttc.or.jp 1-2-11, hamamatsu-cho, minato-ku tokyo 105-0013, japan
temx8 txc-04218 - 225 of 226 - data sheet proprietary transwitch corporation information for use solely by its customers product preview product preview txc-04218-mb, ed. 1 august 2003 - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without not ice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is gr anted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combinati on, machine, or process in which such semiconductor products or se rvices might be or are used.
transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453

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